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december 2002 1/398 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev. 1.3 st92f124/st92f150/st92f250 8/16-bit single voltage flash mcu family with ram, e 3 tm (emulated eeprom), can 2.0b and j1850 blpd preliminary data n memories C internal memory: single voltage flash up to 256 kbytes, ram up to 8kbytes, 1k byte e 3 tm (emulat- ed eeprom) C in-application programming (iap) C 224 general purpose registers (register file) availa- ble as ram, accumulators or index pointers n clock, reset and supply management C register-oriented 8/16 bit core with run, wfi, slow, halt and stop modes C 0-24 mhz operation (int. clock), 4.5-5.5 v range C pll clock generator (3-5 mhz crystal) C minimum instruction time: 83 ns (24 mhz int. clock) n 80, 77 or 48 i/o pins (depending on device) n interrupt management C 80, 77 or 48 i/o pins (depending on device) C 4 external fast interrupts + 1 nmi C up to 16 pins programmable as wake-up or addition- al external interrupt with multi-level interrupt handler C dma controller for reduced processor overhead n timers C 16-bit timer with 8-bit prescaler, and watchdog tim- er (activated by software or by hardware) C 16-bit standard timer that can be used to generate a time base independent of pll clock generator C two 16-bit independent extended function timers (efts) with prescaler, 2 input captures and two output compares (100-pin devices only) C two 16-bit multifunction timers, with prescaler, 2 in- put captures and two output compares n communication interfaces C serial peripheral interface (spi) with selectable master/slave mode C one multiprotocol serial communications interface with asynchronous and synchronous capabilities C one asynchronous serial communications interface (on 100-pin versions only) with 13-bit lin synch break generation capability C j1850 byte level protocol decoder (jblpd) (on f150j versions only) C one or two full i2c multiple master/slave interfaces supporting access bus C one or two can 2.0b (150 version only) active inter- faces n 10-bit analog to digital converter allowing up to 16 input channels on 100-pin devices or 8 input channels on 64-pin devices n development tools C free high performance development environment (ide) based on visual debugger, assembler, linker, and c-compiler; real time operating system (os- ek os, cmx) and can drivers C hardware emulator and flash programming board for development and isp flasher for production device summary 1) see section 12.3 on page 396 for important information 2) see table 70 on page 393 pqfp100 14x20 tqfp64 14x14 tqfp100 14x14 features st92f124r9 st92f124v1 st92f150c(r/v)1 st92f150jdv1 st92f250cv2 flash - bytes 64k 128k 128k 128k 256k ram - bytes 2k 4k 4k 6k 8k e 3 tm - bytes 1k 1k 1k 1k 1k timers and serial interface 2 mft, stim, wd, sci, spi, i2c 2 mft, 2 eft, stim, wd, 2 sci, spi, i2c 2 mft, 0/2 eft, stim, wd, 1/2 sci, spi, i2c 2 mft, 2 eft, stim, wd, 2 sci, spi, i2c 2 mft, 2 eft, stim, wd, 2 sci, spi, 2 i2c 1) adc 8 x 10 bits 16 x 10 bits 8/16 x 10 bits 16 x 10 bits network interface - can 2 can, j1850 can, lin master temp. range -40c to 85c -40c to 105c -40c to 105c , -40c to 125c 2) -40 o c to 125 o c -40c to 105c , -40c to 125c 2) packages tqfp64 pqfp100 p/tqfp100 and tqfp64 p/tqfp100 9
2/398 table of contents 398 9 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 alternate functions for i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.7 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3 single voltage flash & e3 tm (emulated eeprom) . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4 write operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5 protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6 flash in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.2 memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3 st92f124/f150/f250 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 5.2 interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.4 priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.7 standard interrupts (can and sci-a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.8 top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.9 dedicated on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.10 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.11 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.12 wake-up / interrupt lines management unit (wuimu) . . . . . . . . . . . . . . . . 109 6 on-chip direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.2 dma priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3 dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.4 dma cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.5 swap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20
3/398 table of contents 9 6.6 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7 reset and clock control unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 7.2 clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.4 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.5 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.6 reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 external memory interface (extmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 8.2 external memory signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 9.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.1 timer/watchdog (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.2 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.3 extended function timer (eft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 multifunction timer (mft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 10.5 multiprotocol serial communications interface (sci-m) . . . . . . . . . . . 209 10.6 asynchronous serial communications interface (sci-a) . . . . . . . . . . . 234 10.7 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 10.8 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 10.9 j1850 byte level protocol decoder (jblpd) . . . . . . . . . . . . . . . . . . . . . . . . 281 10.10 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 10.11 10-bit analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 11 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 92 12.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 12.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 12.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 13 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7
4/398 st92f124/f150/f250 - general description 1 general description 1.1 introduction the st92f124/f150/f250 microcontroller is de- veloped and manufactured by stmicroelectronics using a proprietary n-well hcmos process. its performance derives from the use of a flexible 256-register programming model for ultra-fast con- text switching and real-time event response. the intelligent on-chip peripherals offload the st9 core from i/o and data management processing tasks allowing critical application tasks to get the maxi- mum use of core resources. the new-generation st9 mcu devices now also support low power consumption and low voltage operation for power- efficient and low-cost embedded systems. 1.1.1 st9+ core the advanced core consists of the central processing unit (cpu), the register file, the inter- rupt and dma controller, and the memory man- agement unit. the mmu allows a single linear ad- dress space of up to 4 mbytes. four independent buses are controlled by the core: a 22-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. the powerful i/o capabilities demanded by micro- controller applications are fulfilled by the st92f150/f124 with 48 (64-pin devices) or 77 (100-pin devices) i/o lines dedicated to digital in- put/output and with 80 i/o lines by the st92f250. these lines are grouped into up to ten 8-bit i/o ports and can be configured on a bit basis under software control to provide timing, status signals, an address/data bus for interfacing to the external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel i/o. two memory spaces are available to support this wide range of configurations: a combined program/ data memory space and the internal register file, which includes the control and status registers of the on-chip peripherals. 1.1.2 external memory interface 100-pin devices have a 22-bit external address bus allowing them to address up to 4m bytes of ex- ternal memory. 64-pin devices have an 11-bit ex- ternal address bus for addressing up to 2k bytes. 1.1.3 on-chip peripherals two 16-bit multifunction timers, each with an 8 bit prescaler and 12 operating modes allow simple use for complex waveform generation and meas- urement, pwm functions and many other system timing functions by the usage of the two associat- ed dma channels for each timer. on 100-pin devices, two extended function tim- ers provide further timing and signal generation capabilities. a standard timer can be used to generate a sta- ble time base independent from the pll. an i 2 c interface (two in the st92f250) provides fast i 2 c and access bus support. the spi is a synchronous serial interface for mas- ter and slave device communication. it supports single master and multimaster systems. a j1850 byte level protocol decoder is available (on some devices only) for communicating with a j1850 network. the bxcan (basic extended) interface supports 2.0b active protocol. it has 3 transmit mailboxes, 2 independent receive fifos and 8 filters. in addition, there is an 16 channel analog to digital converter with integral sample and hold, fast con- version time and 10-bit resolution. in the 64-pin version only 8 input channels are available. there is one multiprotocol serial communications interface with an integral generator, asynchronous and synchronous capability (fully programmable format) and associated address/wake-up option, plus two dma channels. on some devices, there is an additional asynchro- nous serial communications interface. finally, a programmable pll clock generator al- lows the usage of standard 3 to 5 mhz crystals to obtain a large range of internal frequencies up to 24mhz. low power run (slow), wait for inter- rupt, low power wait for interrupt, stop and halt modes are also available. 9
5/398 st92f124/f150/f250 - general description figure 1. st92f124r9: architectural block diagram 256 bytes register file ram 2 kbytes st9 core 8/16 bits cpu interrupt management memory bus rccu register bus watchdog nmi miso mosi sck ss st. timer spi sda scl i 2 c bus sci m flash 64 kbytes txclk rxclk sin dcd sout clkout rts wdout hw0sw1 stout fully prog. i/os p0[7:0] p1[2:0] p2[7:0] p3[7:4] p4[7:4] p5[7:0] p6[5:2,0] p7[7:0] mf timer 0 tinpa0 touta0 tinpb0 toutb0 tinpa1 touta1 tinpb1 toutb1 int[5:0] wkup[13:0] mf timer 1 e 3 tm 1 kbyte oscin oscout reset clock2/8 intclk ck_af adc av dd av ss ain[15:8] extrg v reg voltage regulator the alternate functions ( italic characters ) are mapped on port 0, port 1, port2, port3, port4, port5, port6 and port7. 9
6/398 st92f124/f150/f250 - general description figure 2. st92f124v1: architectural block diagram 256 bytes register file ram 4 kbytes st9 core 8/16 bits cpu interrupt management memory bus rccu ext. mem. address data port0 ext. mem. address ports 1,9 register bus watchdog as ds rw wait nmi ds2 rw* miso mosi sck ss a[10:8] a[21:11] a[7:0] d[7:0] st. timer spi sda scl i 2 c bus flash 128 kbytes wdout hw0sw1 stout fully prog. i/os p0[7:0] p1[7:3] p1[2:0] p2[7:0] p3[7:4] p3[3:1] p4[7:4] p4[3:0] p5[7:0] p6[5:2,0] p6.1 p7[7:0] p8[7:0] p9[7:0] mf timer 0 tinpa0 touta0 tinpb0 toutb0 tinpa1 touta1 tinpb1 toutb1 int[5:0] int6 wkup[13:0] wkup[15:14] mf timer 1 e 3 tm 1 kbyte oscin oscout reset clock2/8 intclk ck_af adc av dd av ss ain[15:8] ain[7:0] extrg v reg voltage regulator the alternate functions ( italic characters ) are mapped on port 0, port 1, port2, port3, port4, port5, port6, port7, port8 and port9. icapa0 ocmpa0 icapb0 ocmpb0 extclk0 icapa1 ocmpa1 icapb1 ocmpb1 extclk1 ef timer 0 ef timer 1 sci m txclk rxclk sin dcd sout clkout rts sci a rdi tdo 9
7/398 st92f124/f150/f250 - general description figure 3. st92f150cv1: architectural block diagram 256 bytes register file ram 4 kbytes st9 core 8/16 bits cpu interrupt management memory bus rccu ext. mem. address data port0 ext. mem. address ports 1,9* register bus watchdog as ds rw wait nmi ds2 rw* miso mosi sck ss a[10:8] a[21:11]* a[7:0] d[7:0] st. timer spi sda scl i 2 c bus flash 128 kbytes wdout hw0sw1 stout * not available on 64-pin version. fully prog. i/os p0[7:0] p1[7:3]* p1[2:0] p2[7:0] p3[7:4] p3[3:1]* p4[7:4] p4[3:0]* p5[7:0] p6[5:2,0] p6.1* p7[7:0] p8[7:0]* p9[7:0]* mf timer 0 tinpa0 touta0 tinpb0 toutb0 tinpa1 touta1 tinpb1 toutb1 int[5:0] int6 * wkup[13:0] wkup[15:14]* mf timer 1 e 3 tm 1 kbyte oscin oscout reset clock2/8 intclk ck_af adc av dd av ss ain[15:8] ain[7:0]* extrg rx0 tx0 can_0 v reg voltage regulator the alternate functions ( italic characters ) are mapped on port 0, port 1, port2, port3, port4, port5, port6, port7, port8* and port9*. icapa0 ocmpa0 icapb0 ocmpb0 extclk0 icapa1 ocmpa1 icapb1 ocmpb1 extclk1 ef timer 0 * ef timer 1 * sci m txclk rxclk sin dcd sout clkout rts sci a* rdi tdo 9
8/398 st92f124/f150/f250 - general description figure 4. st92f150jdv1: architectural block diagram 256 bytes register file st9 core 8/16 bit cpu interrupt management memory bus rccu register bus watchdog as ds rw wait nmi ds2 rw miso mosi sck ss ef timer 0 st. timer spi sci m txclk rxclk sin dcd sout clkout rts wdout hw0sw1 stout icapa0 ocmpa0 icapb0 ocmpb0 extclk0 fully prog. i/os p0[7:0] p1[7:0] p2[7:0] p3[7:1] p4[7:0] p5[7:0] p6[5:0] p7[7:0] p8[7:0] p9[7:0] rdi tdo mf timer 0 tinpa0 touta0 tinpb0 toutb0 icapa1 ocmpa1 icapb1 ocmpb1 extclk1 tinpa1 touta1 tinpb1 toutb1 int[6:0] wkup[15:0] ef timer 1 mf timer 1 sci a oscin oscout reset clock2/8 clock2 intclk ck_af adc av dd av ss ain[15:0] extrg sda scl i 2 c bus vpwi vpwo j1850 jblpd a[7:0] d[7:0] a[21:8] ext. mem. address data port0 ext. mem. address ports 1,9 ram 6 kbytes flash 128 kbytes e 3 tm 1k byte the alternate functions ( italic characters ) are mapped on port0, port1, port2, port3, port4, port5, port6, port7, rx0 tx0 can_0 rx1 tx1 can_1 v reg voltage regulator port8 and port9. rdi tdo flash 128 kbytes 1
9/398 st92f124/f150/f250 - general description figure 5. st92f250cv2: architectural block diagram 256 bytes register file st9 core 8/16 bit cpu interrupt management memory bus rccu register bus watchdog as ds rw wait nmi ds2 rw miso mosi sck ss ef timer 0 st. timer spi sci m txclk rxclk sin dcd sout clkout rts wdout hw0sw1 stout icapa0 ocmpa0 icapb0 ocmpb0 extclk0 fully prog. i/os p0[7:0] p1[7:0] p2[7:0] p3[7:0] p4[7:0] p5[7:0] p6[7:0] p7[7:0] p8[7:0] p9[7:0] rdi tdo mf timer 0 tinpa0 touta0 tinpb0 toutb0 icapa1 ocmpa1 icapb1 ocmpb1 extclk1 tinpa1 touta1 tinpb1 toutb1 int[6:0] wkup[15:0] ef timer 1 mf timer 1 sci a oscin oscout reset clock2/8 clock2 intclk ck_af adc av dd av ss ain[15:0] extrg sda1 scl1 i 2 c bus _1 a[7:0] d[7:0] a[21:8] ext. mem. address data port0 ext. mem. address ports 1,9 ram 8 kbytes flash 256 kbytes e 3 tm 1k byte the alternate functions ( italic characters ) are mapped on port0, port1, port2, port3, port4, port5, port6, port7, rx0 tx0 can_0 v reg voltage regulator port8 and port9. sda0 scl0 i 2 c bus _0 1
10/398 st92f124/f150/f250 - general description 1.2 pin description as . address strobe (output, active low, 3-state). address strobe is pulsed low once at the begin- ning of each memory cycle. the rising edge of as indicates that address, read/write (rw ), and data signals are valid for memory transfers. ds . data strobe (output, active low, 3-state). data strobe provides the timing for data movement to or from port 0 for each memory transfer. during a write cycle, data out is valid at the leading edge of ds . during a read cycle, data in must be valid pri- or to the trailing edge of ds . when the st9 ac- cesses on-chip memory, ds is held high during the whole memory cycle. reset . reset (input, active low). the st9 is ini- tialised by the reset signal. with the deactivation of reset , program execution begins from the program memory location pointed to by the vector contained in program memory locations 00h and 01h. rw . read/write (output, 3-state). read/write de- termines the direction of data transfer for external memory transactions. rw is low when writing to external memory, and high for all other transac- tions. oscin, oscout. oscillator (input and output). these pins connect a parallel-resonant crystal, or an external source to the on-chip clock oscillator and buffer. oscin is the input of the oscillator in- verter; oscout is the output of the oscillator in- verter. hw0sw1. when connected to v dd through a 1k pull-up resistor, the software watchdog option is selected. when connected to v ss through a 1k pull-down resistor, the hardware watchdog option is selected. vpwo . this pin is the output line of the j1850 pe- ripheral (jblpd). it is available only on some de- vices. rx1/wkup6. receive data input of can1 and wake-up line 6. available only on some devices. when the can1 peripheral is disabled, a pull-up resistor is connected internally to this pin. tx1. transmit data output of can1. available on some devices. p0[7:0], p1[7:0] or p9[7:2] (input/output, ttl or cmos compatible) . 11 lines (64-pin devices) or 22 lines (100-pin devices) providing the external memory interface for addressing 2k or 4m bytes of external memory. p0[7:0], p1[2:0], p2[7:0], p3[7:4], p4.[7:4], p5[7:0], p6[5:2,0], p7[7:0] i/o port lines (input/ output, ttl or cmos compatible) . i/o lines grouped into i/o ports of 8 bits, bit programmable under software control as general purpose i/o or as alternate functions. p1[7:3], p3[3:1], p4[3:0], p6.1, p8[7:0], p9[7:0] additional i/o port lines available on 100-pin ver- sions only. p3.0, p6[7:6] additional i/o port lines available on st92f250 version only. av dd . analog v dd of the analog to digital con- verter (common for adc 0 and adc 1). avdd can be switched off when the adc is not in use. av ss . analog v ss of the analog to digital con- verter (common for adc 0 and adc 1). v dd . main power supply voltage. four pins are available on 100-pin versions, two on 64-pin ver- sions. the pins are internally connected. v ss . digital circuit ground. four pins are availa- ble on 100-pin versions, two on 64-pin versions. the pins are internally connected. v test power supply voltage for flash test pur- poses. this pin must be kept to 0 in user mode. v reg . stabilization capacitors for the internal volt- age regulator. the user must connect external sta- bilization capacitors to these pins. refer to figure 16 . 1.2.1 electromagnetic compatibility (emc) to reduce the electromagnetic interference the fol- lowing features have been implemented: C a low power oscillator is included with a control- led gain to reduce emi and the power consump- tion. C two or four pairs of digital power supply pins (v dd , v ss ) are located on each side of the 100- pin package (2 pairs on 64-pin package). C digital and analog power supplies are complete- ly separated. C digital power supplies for internal logic and i/o ports are separated internally. C digital power supplies managed by internal volt- age regulator note: each pair of digital v dd /v ss pins should be externally connected by a 10 m f tantalum capaci- tor and a 100 nf ceramic capacitor. 1.2.2 i/o port alternate functions each pin of the i/o ports of the st92f124/f150/ f250 may assume software programmable alter- nate functions as shown in section 1.4 . 9
11/398 st92f124/f150/f250 - general description 1.2.3 termination of unused pins the st9 device is implemented using cmos tech- nology; therefore unused pins must be properly terminated in order to avoid application reliability problems. in fact, as shown in figure 6 , the stand- ard input circuitry is based on the cmos inverter structure. figure 6. cmos basic inverter when an input is kept at logic zero, the n-channel transistor is off, while the p-channel is on and can conduct. the opposite occurs when an input is kept at logic one. cmos transistors are essentially linear devices with relatively broad switching points. during commutation, the input passes through midsupply, and there is a region of input voltage values where both p and n-channel tran- sistors are on. since normally the transitions are fast, there is a very short time in which a current can flow: once the switching is completed there is no longer current. this phenomenon explains why the overall current depends on the switching rate: the consumption is directly proportional to the number of transistors inside the device which are in the linear region during transitions, charging and discharging internal capacitances. in order to avoid extra power supply current, it is important to bias input pins properly when not used. in fact, if the input impedance is very high, pins can float, when not connected, either to a midsupply level or can oscillate (injecting noise in the device). depending on the specific configuration of each i/o pin on different st9 devices, it can be more or less critical to leave unused pins floating. for this reason, on most pins, the configuration after re- set enables an internal weak pull-up transistor in order to avoid floating conditions. for other pins this is intrinsically forbidden, like for the true open- drain pins. in any case, the application software must program the right state for unused pins to avoid conflicts with external circuitry (whichever it is: pull-up, pull-down, floating, etc.). the suggested method of terminating unused i/o is to connect an external individual pull-up or pull- down for each pin, even though initialization soft- ware can force outputs to a specified and defined value, during a particular phase of the r eset rou- tine there could be an undetermined status at the input section. usage of pull-ups and/or pull-downs is preferable in place of direct connection to v dd or v ss . if pull- up or pull-down resistors are used, inputs can be forced for test purposes to a different value, and outputs can be programmed to both digital levels without generating high current drain due to the conflict. anyway, during system verification flow, attention must be paid to reviewing the connection of each pin, in order to avoid potential problems. 1.2.4 avoidance of pin damage although integrated circuit data sheets provide the user with conservative limits and conditions in or- der to prevent damage, sometimes it is useful for the hardware system designer to know the internal failure mechanisms: the risk of exposure to illegal voltages and conditions can be reduced by smart protection design. it is not possible to classify and to predict all the possible damage resulting from violating maxi- mum ratings and conditions, due to the large number of variables that come into play in defining the failures: in fact, when an overvoltage condition is applied, the effects on the device can vary sig- nificantly depending on lot-to-lot process varia- tions, operating temperature, external interfacing of the st9 with other devices, etc. in the following sections, background technical in- formation is given in order to help system design- ers to reduce risk of damage to the st9 device. 1.2.4.1 electrostatic discharge and latchup cmos integrated circuits are generally sensitive to exposure to high voltage static electricity, which can induce permanent damage to the device: a typical failure is the breakdown of thin oxides, which causes high leakage current and sometimes shorts. latchup is another typical phenomenon occurring in integrated circuits: unwanted turning on of para- sitic bipolar structures, or silicon-controlled rectifi- p n in out v dd v ss 9
12/398 st92f124/f150/f250 - general description ers (scr), may overheat and rapidly destroy the device. these unintentional structures are com- posed of p and n regions which work as emitters, bases and collectors of parasitic bipolar transis- tors: the bulk resistance of the silicon in the wells and substrate act as resistors on the scr struc- ture. applying voltages below v ss or above v dd , and when the level of current is able to generate a voltage drop across the scr parasitic resistor, the scr may be turned on; to turn off the scr it is necessary to remove the power supply from the device. the present st9 design implements layout and process solutions to decrease the effects of elec- trostatic discharges (esd) and latchup. of course it is not possible to test all devices, due to the de- structive nature of the mechanism; in order to guarantee product reliability, destructive tests are carried out on groups of devices, according to stmicroelectronics internal quality assurance standards and recommendations. 1.2.4.2 protective interface although st9 input/output circuitry has been de- signed taking esd and latchup problems into ac- count, for those applications and systems where st9 pins are exposed to illegal voltages and high current injections, the user is strongly recommend- ed to implement hardware solutions which reduce the risk of damage to the microcontroller: low-pass filters and clamp diodes are usually sufficient in preventing stress conditions. the risk of having out-of-range voltages and cur- rents is greater for those signals coming from out- side the system, where noise effect or uncon- trolled spikes could occur with higher probability than for the internal signals; it must be underlined that in some cases, adoption of filters or other ded- icated interface circuitries might affect global mi- crocontroller performance, inducing undesired tim- ing delays, and impacting the global system speed. figure 7. digital input/output - push-pull pin output buffer p n p n n input buffer p esd protection circuitry port circuitry i/o circuitry p en en 9
13/398 st92f124/f150/f250 - general description 1.2.4.3 internal circuitry: digital i/o pin in figure 7 a schematic representation of an st9 pin able to operate either as an input or as an out- put is shown. the circuitry implements a standard input buffer and a push-pull configuration for the output buffer. it is evident that although it is possi- ble to disable the output buffer when the input sec- tion is used, the mos transistors of the buffer itself can still affect the behaviour of the pin when ex- posed to illegal conditions. in fact, the p-channel transistor of the output buffer implements a direct diode to v dd (p-diffusion of the drain connected to the pin and n-well connected to v dd ), while the n- channel of the output buffer implements a diode to v ss (p-substrate connected to vss and n-diffu- sion of the drain connected to the pin). in parallel to these diodes, dedicated circuitry is implemented to protect the logic from esd events (mos, diodes and input series resistor). the most important characteristic of these extra devices is that they must not disturb normal oper- ating modes, while acting during exposure to over limit conditions, avoiding permanent damage to the logic circuitry. all i/o pins can generally be programmed to work also as open-drain outputs, by simply writing in the corresponding register of the i/o port. the gate of the p-channel of the output buffer is disabled: it is important to highlight that physically the p-channel transistor is still present, so the diode to v dd works. in some applications it can occur that the voltage applied to the pin is higher than the v dd value (supposing the external line is kept high, while the st9 power supply is turned off): this con- dition will inject current through the diode, risking permanent damages to the device. in any case, programming i/o pins as open-drain can help when several pins in the system are tied to the same point: of course software must pay at- tention to program only one of them as output at any time, to avoid output driver contentions; it is advisable to configure these pins as output open- drain in order to reduce the risk of current conten- tions. figure 8. digital input/output - true open drain output pin output buffer n p n n input buffer esd protection circuitry port circuitry i/o circuitry p en en 9
14/398 st92f124/f150/f250 - general description in figure 8 a true open-drain pin schematic is shown. in this case all paths to v dd are removed (p-channel driver, esd protection diode, internal weak pull-up) in order to allow the system to turn off the power supply of the microcontroller and keep the voltage level at the pin high without in- jecting current in the device. this is a typical con- dition which can occur when several devices inter- face a serial bus: if one device is not involved in the communication, it can be disabled by turning off its power supply to reduce the system current consumption. when an illegal negative voltage level is applied to the st9 i/o pins (both versions, push-pull and true open-drain output) the clamp diode is always present and active (see esd protection circuitry and n-channel driver). 1.2.4.4 internal circuitry: analog input pin figure 9 shows the internal circuitry used for ana- log input. it is substantially a digital i/o with an added analog multiplexer for the selection of the input channel of the analog to digital converter (adc). the presence of the multiplexer p-channel and n- channel can affect the behaviour of the pin when exposed to illegal voltage conditions. these tran- sistors are controlled by a low noise logic, biased through av dd and av ss including p-channel n- well: it is important to always verify the input volt- age value with respect to both analog power sup- ply and digital power supply, in order to avoid un- intended current injections which (if not limited) could destroy the device. figure 9. digital input/output - push-pull output - analog multiplexer input pin output buffer p n p n n input buffer p e sd protection circuitry port circuitry i/o circuitry p en en n p p 9
15/398 st92f124/f150/f250 - general description 1.2.4.5 power supply and ground as already said for the i/o pins, in order to guaran- tee st9 compliancy with respect to quality assur- ance recommendations concerning esd and latchup, dedicated circuits are added to the differ- ent power supply and ground pins (digital and an- alog). these structures create preferred paths for the high current injected during discharges, avoid- ing damage to active logic and circuitry. it is impor- tant for the system designer to take this added cir- cuitry into account, which is not always transpar- ent with respect to the relative level of voltages ap- plied to the different power supply and ground pins. figure 10 shows schematically the protection net implemented on st9 devices, composed of di- odes and other special structures. the clamp structure between the v dd and v ss pins is designed to be active during very fast tran- sitions (typical of electrostatic discharges). other paths are implemented through diodes: they limit the possibility of positively differentiating av dd and v dd (i.e. av dd > v dd ); similar considerations are valid for av ss and v ss due to the back-to- back diode structure implemented between the two pins. anyway, it must be highlighted that, be- cause v ss and av ss are connected to the sub- strate of the silicon die (even though in different ar- eas of the die itself), they represent the reference point from which all other voltages are measured, and it is recommended to never differentiate av ss from v ss . note: if more than one pair of pins for v ss and v dd is available on the device, they are connected internally and the protection net diagram remains the same as shown in figure 10 . figure 10. power supply and ground configuration n p p n v dd v ss av dd av ss v test 9
16/398 st92f124/f150/f250 - general description figure 11. st92f124/st92f150: pin configuration (top-view tqfp64) tx0*/wait /wkup5/p5.0 rx0*/wkup6/wdout/p5.1 sin/wkup2/p5.2 wdin/sout/p5.3 txclk/clkout/p5.4 rxcl0/wkup7/p5.5 dcd/wkup8/p5.6 wkup9/rts/p5.7 wkup4/p4.4 extrg/stout/p4.5 sda/p4.6 wkup1/scl/p4.7 s s /p3.4 miso/p3.5 mosi/p3.6 sck/wkup0/p3.7 hw0sw1 reset oscout oscin v dd v ss p7.7/ain15/wkup13 p7.6/ain14/wkup12 p7.5/ain13/wkup11 p7.4/ain12/wkup3 p7.3/ain11 p7.2/ain10 p7.1/ain9 p7.0/ain8 / ck_af av ss av dd n.c p6.5/wkup10/intclk p6.4/nmi p6.3/int3/int5 p6.2/int2/int4 p6.0/int0/int1/clock2/8 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 reserved** reserved** reserved** tinpa0/p2.0 tinpb0/p2.1 touta0/p2.2 toutb0/p2.3 tinpa1/p2.4 tinpb1/p2.5 touta1/p2.6 toutb1/p2.7 v ss v dd v reg v test p1.0 p1.1 p1.2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 st92f124 / * not available on st92f124 version st92f150 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 * * reserved for st tests, must be left unconnected 9
17/398 st92f124/f150/f250 - general description figure 12. st92f150: pin configuration (top-view pqfp100) a17/p9.3 a18/p9.4 a19/p9.5 a20/p9.6 a21/p9.7 tx0/wait /wkup5/p5.0 rx0/wkup6/wdout/p5.1 sin/wkup2/p5.2 wdin/sout/p5.3 txclk/clkout/p5.4 rxclk/wkup7/p5.5 dcd/wkup8/p5.6 wkup9/rts/p5.7 icapa1/p4.0 clock2/p4.1 ocmpa1/p4.2 v ss v dd icapb1/ocmpb1/p4.3 extclk1/wkup4/p4.4 extrg/stout/p4.5 sda/p4.6 wkup1/scl/p4.7 icapb0/p3.1 icapa0/ocmpa0/p3.2 ocmpb0/p3.3 extclk0/ss /p3.4 miso/p3.5 mosi/p3.6 sck/wkup0/p3.7 p9.2/a16 p9.1/tdo p9.0/rdi hw0sw1 reset oscout oscin v dd v ss p7.7/ain15/7/wkup13 p7.6/ain14/wkup12 p7.5/ain13/wkup11 p7.4/ain12/wkup3 p7.3/ain11 p7.2/ain10 p7.1/ain9 p7.0/ain8 / ck_af av ss av dd p8.7/ain7 p8.6/ain6 p8.5/ain5 p8.4/ain4 p8.3/ain3 p8.2/ain2 p8.1/ain1/wkup15 p8.0/ain0/wkup14 vpwo* p6.5/wkup10/intclk/vpw p6.4/nmi p6.3/int3/int5 p6.2/int2/int4/ds2 p6.1/int6/rw p6.0/int0/int1/clock2/8 p0.7/a7/d7 v dd v ss p0.6/a6/d6 p0.5/a5/d5 p0.4/a4/d4 p0.3/a3/d3 p0.2/a2/d2 p0.1/a1/d1 p0.0/a0/d0 as ds p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 v reg rw tinpa0/p2.0 tinpb0/p2.1 touta0/p2.2 toutb0/p2.3 tinpa1/p2.4 tinpb1/p2.5 touta1/p2.6 toutb1/p2.7 v ss v dd v reg v test a8/p1.0 a9/p1.1 a10/p1.2 a11/p1.3 **rx1/wkup6 **tx1 1 50 30 st92f150 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 80 51 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 *on devices without jpbld peripheral, this pin must not be connected. **on devices without can1 peripheral, these pins must not be connected. 9
18/398 st92f124/f150/f250 - general description figure 13. st92f150: pin configuration (top-view tqfp100) * v test must be kept low in standard operating mode. **on devices without can1 peripheral, these pins must not be connected. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 st92f150 p8.4/ain4 p8.3/ain3 p8.2/ain2 p8.1/ain1/wkup15 p8.0/ain0/wkup14 vpwo p6.5/wkup10/intclk/vpw p6.4/nmi p6.3/int3/int5 p6.2/int2/int4/ds2 p6.1/int6/rw p6.0/int0/int1/clock2/8 p0.7/a7/d7 v dd v ss p0.6/a6/d6 p0.5/a5/d5 p0.3/a3/d3 p0.2/a2/d2 p0.1/a1/d1 p0.0/a0/d0 as ds p0.4/a4/d4 p1.7/a15 a20/p9.6 tx0/wait /wkup5/p5.0 rx0/wkup6/wdout/p5.1 txclk/clkout/p5.4 ocmpa1/p4.2 v dd a21/p9.7 wdin/sout/p5.3 dcd/wkup8/p5.6 v ss icapb1/ocmpb1/p4.3 sda/p4.6 sin/wkup2/p5.2 rxclk/wkup7/p5.5 clock2/p4.1 extclk1/wkup4/p4.4 icapb0/p3.1 icapa0/ocmpa0/p3.2 wkup9/rts/p5.7 icapa1/p4.0 extrg/stout/p4.5 wkup1/scl/p4.7 ocmpb0/p3.3 extclk0/ss /p3.4 miso/p3.5 p9.5/a19 p9.4/a18 p9.2/a16 hw0sw1 p7.7/ain15/7/wkup13 p7.4/ain12/wkup3 p9.3/a17 p9.0/rdi reset p7.6/ain14/wkup12 p7.5/ain13/wkup11 p7.1/ain9 p9.1/tdo oscin v ss p7.3/ain11 p7.0/ain8/ck_af p8.7/ain7 oscout v dd p7.2/ain10 av ss av dd p8.6/ain6 p8.5/ain5 mosi/p3.6 sck/wkup0/p3.7 rw touta0/p2.2 v ss *v test v reg tinpb0/p2.1 toutb0/p2.3 v dd v reg a10/p1.2 tinpa0/p2.0 tinpb1/p2.5 toutb1/p2.7 a8/p1.0 a11/p1.3 a12/p1.4 tinpa1/p2.4 touta1/p2.6 a9/p1.1 **rx1/wkup6 **tx1 a13/p1.5 a14/p1.6 9
19/398 st92f124/f150/f250 - general description figure 14. st92f250: pin configuration (top-view pqfp100) * v test must be kept low in standard operating mode. sda1/a17/p9.3 scl1/a18/p9.4 a19/p9.5 a20/p9.6 a21/p9.7 tx0/wait /wkup5/p5.0 rx0/wkup6/wdout/p5.1 sin/wkup2/p5.2 wdin/sout/p5.3 txclk/clkout/p5.4 rxclk/wkup7/p5.5 dcd/wkup8/p5.6 wkup9/rts/p5.7 icapa1/p4.0 clock2/p4.1 ocmpa1/p4.2 v ss v dd icapb1/ocmpb1/p4.3 extclk1/wkup4/p4.4 extrg/stout/p4.5 sda0/p4.6 wkup1/scl0/p4.7 icapb0/p3.1 icapa0/ocmpa0/p3.2 ocmpb0/p3.3 extclk0/ss /p3.4 miso/p3.5 mosi/p3.6 sck/wkup0/p3.7 p9.2/a16 p9.1/tdo p9.0/rdi hw0sw1 reset oscout oscin v dd v ss p7.7/ain15/7/wkup13 p7.6/ain14/wkup12 p7.5/ain13/wkup11 p7.4/ain12/wkup3 p7.3/ain11 p7.2/ain10 p7.1/ain9 p7.0/ain8/ck_af av ss av dd p8.7/ain7 p8.6/ain6 p8.5/ain5 p8.4/ain4 p8.3/ain3 p8.2/ain2 p8.1/ain1/wkup15 p8.0/ain0/wkup14 p3.0 p6.5/wkup10/intclk p6.4/nmi p6.3/int3/int5 p6.2/int2/int4/ds2 p6.1/int6/rw p6.0/int0/int1/clock2/8 p0.7/a7/d7 v dd v ss p0.6/a6/d6 p0.5/a5/d5 p0.4/a4/d4 p0.3/a3/d3 p0.2/a2/d2 p0.1/a1/d1 p0.0/a0/d0 as ds p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 v reg rw tinpa0/p2.0 tinpb0/p2.1 touta0/p2.2 toutb0/p2.3 tinpa1/p2.4 tinpb1/p2.5 touta1/p2.6 toutb1/p2.7 v ss v dd v reg *v test a8/p1.0 a9/p1.1 a10/p1.2 a11/p1.3 p6.6 p6.7 1 50 30 st92f250 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 80 51 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 9
20/398 st92f124/f150/f250 - general description figure 15. st92f250: pin configuration (top-view tqfp100) * v test must be kept low in standard operating mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 st92f250 p8.4/ain4 p8.3/ain3 p8.2/ain2 p8.1/ain1/wkup15 p8.0/ain0/wkup14 p3.0 p6.5/wkup10/intclk p6.4/nmi p6.3/int3/int5 p6.2/int2/int4/ds2 p6.1/int6/rw p6.0/int0/int1/clock2/8 p0.7/a7/d7 v dd v ss p0.6/a6/d6 p0.5/a5/d5 p0.3/a3/d3 p0.2/a2/d2 p0.1/a1/d1 p0.0/a0/d0 as ds p0.4/a4/d4 p1.7/a15 a20/p9.6 tx/wait /wkup5/p5.0 rx/wkup6/wdout/p5.1 txclk/clkout/p5.4 ocmpa1/p4.2 v dd a21/p9.7 wdin/sout/p5.3 dcd/wkup8/p5.6 v ss icapb1/ocmpb1/p4.3 sda0/p4.6 sin/wkup2/p5.2 rxclk/wkup7/p5.5 clock2/p4.1 extclk1/wkup4/p4.4 icapb0/p3.1 icapa0/ocmpa0/p3.2 wkup9/rts/p5.7 icapa1/p4.0 extrg/stout/p4.5 wkup1/scl0/p4.7 ocmpb0/p3.3 extclk0/ss /p3.4 miso/p3.5 p9.5/a19 p9.4/a18/scl1 p9.2/a16 hw0sw1 p7.7/ain15/7/wkup13 p7.4/ain12/wkup3 p9.3/a17/sda1 p9.0/rdi reset p7.6/ain14/wkup12 p7.5/ain13/wkup11 p7.1/ain9 p9.1/tdo oscin v ss p7.3/ain11 p7.0/ain8/ck_af p8.7/ain7 oscout v dd p7.2/ain10 av ss av dd p8.6/ain6 p8.5/ain5 mosi/p3.6 sck/wkup0/p3.7 rw touta0/p2.2 v ss *v test v reg tinpb0/p2.1 toutb0/p2.3 v dd v reg a10/p1.2 tinpa0/p2.0 tinpb1/p2.5 toutb1/p2.7 a8/p1.0 a11/p1.3 a12/p1.4 tinpa1/p2.4 touta1/p2.6 a9/p1.1 p6.6 p6.7 a13/p1.5 a14/p1.6 9
21/398 st92f124/f150/f250 - general description table 1. st92f124/f150/f250 power supply pins table 2. st92f124/f150/f250 primary function pins note 1: st92f150jdv1 only. name function tqfp64 pqfp100 tqfp100 v dd main power supply voltage (pins internally connected) -1815 27 42 39 -6562 60 93 90 v ss digital circuit ground (pins internally connected) -1714 26 41 38 -6461 59 92 89 av dd analog circuit supply voltage 49 82 79 av ss analog circuit ground 50 83 80 v test must be kept low in standard operating mode 29 44 41 v reg stabilization capacitor(s) for internal voltage regulator 28 31 43 28 40 name function tqfp64 pqfp100 tqfp100 as address strobe - 56 53 ds data strobe - 55 52 rw read/write - 32 29 oscin crystal oscillator input 61 94 91 oscout crystal oscillator output 62 95 92 reset reset to initialize the microcontroller 63 96 93 hw0sw1 watchdog hw/sw enabling selection 64 97 94 vpwo 1) j1850 jblpd output - 73 70 rx1/wkup6 1) can1 receive data / wake-up line 6 - 49 46 tx1 1) can1 transmit data. - 50 47 9
22/398 st92f124/f150/f250 - general description 1.3 voltage regulator the internal voltage regulator (vr) is used to power the microcontroller starting from the exter- nal power supply. the vr comprises a main volt- age regulator and a low-power regulator. C the main voltage regulator generates sufficient current for the microcontroller to operate in any mode. it has a static power consumption (300 a typ.). C the separate low-power regulator consumes less power is used only when the microcontrol- ler is in low power mode. it has a different de- sign from the main vr and generates a lower, non-stabilized and non-thermally-compensated voltage sufficient for maintaining the data in ram and the register file. for both the main vr and the low-power vr, sta- bilization is achieved by an external capacitor, connected to one of the v reg pins. the minimum recommended value is 300 nf, and care must be taken to minimize distance between the chip and the capacitor. care should also be taken to limit the serial inductance to less than 60nh. figure 16. recommended connections for v reg important: the v reg pin cannot be used to drive external devices. figure 17. minimum required connections for v reg note: pin 31 of pqfp100 or pin 28 of tqfp100 can be left unconnnected. a secondary stabilization net- work can also be connected to these pins. pqfp100 qfp64 c l l = ferrite bead for emi protection. pin 28 c l pin 43 pin 31 tqfp100 c l pin 40 pin 28 suggested type: murata blm18be601fh1: (imp. 600 w at 100 mhz). c = 300 to 600nf c pqfp100 qfp64 c pin 43 pin 31 pin 28 c tqfp100 pin 40 pin 28 c = 300 to 600nf 9
23/398 st92f124/f150/f250 - general description 1.4 i/o ports port 0, port 1 and port 9[7:2] provide the external memory interface. all the ports of the device can be programmed as input/output or in input mode, compatible with ttl or cmos levels (except where schmitt trigger is present). each bit can be programmed individually (refer to the i/o ports chapter). internal weak pull-up as shown in table 3 , not all input sections imple- ment a weak pull-up. this means that the pull-up must be connected externally when the pin is not used or programmed as bidirectional. ttl/cmos input for all those port bits where no input schmitt trig- ger is implemented, it is always possible to pro- gram the input level as ttl or cmos compatible by programming the relevant pxc2.n control bit. refer i/o ports chapter to the section titled input/ output bit configuration. schmitt trigger input two different kinds of schmitt trigger circuitries are implemented: standard and high hysteresis. standard schmitt trigger is widely used (see ta- ble 3 ), while the high hysteresis schmitt trigger is present on ports p4[7:6] and p6[5:4]. all inputs which can be used for detecting interrupt events have been configured with a standard schmitt trigger, apart from the nmi pin which im- plements the high hysteresis version. in this way, all interrupt lines are guaranteed as level sensitive. push-pull/od output the output buffer can be programmed as push- pull or open-drain: attention must be paid to the fact that the open-drain option corresponds only to a disabling of p-channel mos transistor of the buffer itself: it is still present and physically con- nected to the pin. consequently it is not possible to increase the output voltage on the pin over v dd +0.3 volt, to avoid direct junction biasing. pure open-drain output the user can increase the voltage on an i/o pin over v dd +0.3 volt where the p-channel mos tran- sistor is physically absent: this is allowed on all pure open drain pins. in this case, the push-pull option is not available and any weak pull-up must be implemented externally. table 3. i/o port characteristics legend: wpu = weak pull-up, od = open drain. note 1: port 3.0 and port6 [7:6] present on st92f250 version only. input output weak pull-up reset state port 0[7:0] ttl/cmos push-pull/od no bidirectional port 1[7:0] ttl/cmos push-pull/od no bidirectional port 2[1:0] port 2[3:2] port 2[5:4] port 2[7:6] schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od pure od push-pull/od push-pull/od yes no yes yes input input cmos input input cmos port 3[2:0] 1) port 3.3 port 3[7:4] schmitt trigger ttl/cmos schmitt trigger push-pull/od push-pull/od push-pull/od yes yes yes input input cmos input port 4.0, port 4.4 port 4.1 port 4.2, port 4.5 port 4.3 port 4[7:6] schmitt trigger schmitt trigger ttl/cmos schmitt trigger high hysteresis schmitt trigger push-pull/od push-pull/od push-pull/od push-pull/od pure od no yes yes yes no input bidirectional wpu input cmos input input port 5[2:0], port 5[7:4] port 5.3 schmitt trigger ttl/cmos push-pull/od push-pull/od no yes input input cmos port 6[3:0] port 6[5:4] port 6[7:6] 1) schmitt trigger high hysteresis schmitt trigger schmitt trigger push-pull/od push-pull/od push-pull/od yes yes yes input input input port 7[7:0] schmitt trigger push-pull/od yes input port 8[1:0] port 8[7:2] schmitt trigger schmitt trigger push-pull/od push-pull/od yes yes input bidirectional wpu port 9[7:0] schmitt trigger push-pull/od yes bidirectional wpu 9
24/398 st92f124/f150/f250 - general description how to configure the i/o ports to configure the i/o ports, use the information in table 3 , table 4 and the port bit configuration ta- ble in the i/o ports chapter (see page 149 ). input note = the hardware characteristics fixed for each port line in table 3 . C if input note = ttl/cmos, either ttl or cmos input level can be selected by software. C if input note = schmitt trigger, selecting cmos or ttl input by software has no effect, the input will always be schmitt trigger. alternate functions (af) = more than one af cannot be assigned to an i/o pin at the same time: an alternate function can be selected as follows. af inputs: C af is selected implicitly by enabling the corre- sponding peripheral. exception to this are adc inputs which must be explicitly selected as af in- put by software. af outputs or bidirectional lines: C in the case of outputs or i/os, af is selected ex- plicitly by software. example 1: sci-m input af: sin, port: p5.2. schmitt trigger input. write the port configuration bits: p5c2.2=1 p5c1.2=0 p5c0.2 =1 enable the sci peripheral by software as de- scribed in the sci chapter. example 2: sci-m output af: sout, port: p5.3, push-pull/od output. write the port configuration bits (for af out pp): p5c2.3=0 p5c1.3=1 p5c0.3 =1 example 3: external memory i/o af: a0/d0, port : p0.0, input note: ttl/cmos in- put. write the port configuration bits: p0c2.0=1 p0c1.0=1 p0c0.0 =1 example 4: analog input af: ain8, port : 7.0, analog input. write the port configuration bits: p7c2.0=1 p7c1.0=1 p7c0.0 =1 9
25/398 st92f124/f150/f250 - general description 1.5 alternate functions for i/o ports all the ports in the following table are useable for general purpose i/o (input, output or bidirectional). table 4. i/o port alternate functions port name pin no. alternate functions tqfp64 pqfp100 tqfp100 p0.0 - 57 54 a0/d0 i/o address/data bit 0 p0.1 - 58 55 a1/d1 i/o address/data bit 1 p0.2 - 59 56 a2/d2 i/o address/data bit 2 p0.3 - 60 57 a3/d3 i/o address/data bit 3 p0.4 - 61 58 a4/d4 i/o address/data bit 4 p0.5 - 62 59 a5/d5 i/o address/data bit 5 p0.6 - 63 60 a6/d6 i/o address/data bit 6 p0.7 - 66 63 a7/d7 i/o address/data bit 7 p1.0 - 45 42 a8 i/o address bit 8 p1.1 - 46 43 a9 i/o address bit 9 p1.2 - 47 44 a10 i/o address bit 10 p1.3 - 48 45 a11 i/o address bit 11 p1.4 - 51 48 a12 i/o address bit 12 p1.5 - 52 49 a13 i/o address bit 13 p1.6 - 53 50 a14 i/o address bit 14 p1.7 - 54 51 a15 i/o address bit 15 p2.0 18 33 30 tinpa0 i multifunction timer 0 - input a p2.1 19 34 31 tinpb0 i multifunction timer 0 - input b p2.2 20 35 32 touta0 o multifunction timer 0 - output a p2.3 21 36 33 toutb0 o multifunction timer 0 - output b p2.4 22 37 34 tinpa1 i multifunction timer 1 - input a p2.5 23 38 35 tinpb1 i multifunction timer 1 - input b p2.6 24 39 36 touta1 o multifunction timer 1 - output a p2.7 25 40 37 toutb1 o multifunction timer 1 - output b p3.0 1) -7370 p3.1 - 24 21 icapb0 i ext. timer 0 - input capture b p3.2 - 25 22 icapa0 i ext. timer 0 - input capture a ocmpa0 o ext. timer 0 - output compare a p3.3 - 26 23 ocmpb0 o ext. timer 0 - output compare b p3.4 - 27 24 extclk0 i ext. timer 0 - input clock ss i spi - slave select p3.5 14 28 25 miso i/o spi - master input/slave output data p3.6 15 29 26 mosi i/o spi - master output/slave input data 9
26/398 st92f124/f150/f250 - general description p3.7 16 30 27 sck i spi - serial input clock wkup0 i wake-up line 0 sck o spi - serial output clock p4.0 - 14 11 icapa1 i ext. timer 1 - input capture a p4.1 - 15 12 clock2 o clock2 internal signal p4.2 - 16 13 ocmpa1 o ext. timer 1 - output compare a p4.3 - 19 16 icapb1 i ext. timer 1 - input capture b ocmpb1 o ext. timer 1 - output compare b p4.4 - 20 17 extclk1 i ext. timer 1 - input clock wkup4 i wake-up line 4 p4.5 10 21 18 extrg i adc ext. trigger stout o standard timer output p4.6 11 22 19 sda0 i/o i 2 c 0 data p4.7 12 23 20 wkup1 i wake-up line 1 scl0 i/o i 2 c 0 clock p5.0 1 6 3 wait i external wait request wkup5 i wake-up line 5 tx0 1) o can 0 output p5.1 2 7 4 wkup6 i wake-up line 6 rx0 1) i can 0 input wdout o watchdog timer output p5.2 3 8 5 sin0 i sci-m - serial data input wkup2 i wake-up line 2 p5.3 4 9 6 wdin i watchdog timer input sout o sci-m - serial data output p5.4 5 10 7 txclk i sci-m - transmit clock input clkout o sci-m - clock output p5.5 6 11 8 rxclk i sci-m - receive clock input wkup7 i wake-up line 7 p5.6 7 12 9 dcd i sci-m - data carrier detect wkup8 i wake-up line 8 p5.7 8 13 10 wkup9 i wake-up line 9 rts o sci-m - request to send p6.0 43 67 64 int0 i external interrupt 0 int1 i external interrupt 1 clock2/8 o clock2 divided by 8 p6.1 - 68 65 int6 i external interrupt 6 rw o read/write port name pin no. alternate functions tqfp64 pqfp100 tqfp100 9
27/398 st92f124/f150/f250 - general description p6.2 44 69 66 int2 i external interrupt 2 int4 i external interrupt 4 ds2 o data strobe 2 p6.3 45 70 67 int3 i external interrupt 3 int5 i external interrupt 5 p6.4 46 71 68 nmi i non maskable interrupt p6.5 47 72 69 wkup10 i wake-up line 10 vpwi 1) i jblpd input intclk o internal main clock p6.6 1) -4946 p6.7 1) -5047 p7.0 51 84 81 ain8 i analog data input 8 ck_af i clock alternative source p7.1 52 85 82 ain9 i analog data input 9 p7.2 53 86 83 ain10 i analog data input 10 p7.3 54 87 84 ain11 i analog data input 11 p7.4 55 88 85 wkup3 i wake-up line 3 ain12 i analog data input 12 p7.5 56 89 86 ain13 i analog data input 13 wkup11 i wake-up line 11 p7.6 57 90 87 ain14 i analog data input14 wkup12 i wake-up line 12 p7.7 58 91 88 ain15 i analog data input 15 wkup13 i wake-up line 13 p8.0 - 74 71 ain0 i analog data input 0 wkup14 i wake-up line 14 p8.1 - 75 72 ain1 i analog data input 1 wkup15 i wake-up line 15 p8.2 - 76 73 ain2 i analog data input 2 p8.3 - 77 74 ain3 i analog data input 3 p8.4 - 78 75 ain4 i analog data input 4 p8.5 - 79 76 ain5 i analog data input 5 p8.6 - 80 77 ain6 i analog data input 6 p8.7 - 81 78 ain7 i analog data input 7 p9.0 - 98 95 rdi 1) i sci-a receive data input p9.1 - 99 96 tdo 1) o sci-a transmit data output p9.2 - 100 97 a16 o address bit 16 port name pin no. alternate functions tqfp64 pqfp100 tqfp100 9
28/398 st92f124/f150/f250 - general description note 1: available on some devices only. note 2: for the st92f250 device, since a[18:17] share the same pins as sda1 and scl1 of i2c_1, these address bits are not available when the i2c_1 is in use (when i2ccr.pe bit is set). p9.3 - 1 98 a17 2) o address bit 17 sda1 1) i/o i2c 1 data p9.4 - 2 99 a18 2) o address bit 18 scl1 1) i/o i2c 1 clock p9.5 - 3 100 a19 o address bit 19 p9.6 - 4 1 a20 o address bit 20 p9.7 - 5 2 a21 o address bit 21 port name pin no. alternate functions tqfp64 pqfp100 tqfp100 9
29/398 st92f124/f150/f250 - general description 1.6 operating modes to optimize the performance versus the power consumption of the device, the st92f124/f150/ f250 supports different operating modes that can be dynamically selected depending on the per- formance and functionality requirements of the ap- plication at a given moment. run mode : this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). slow mode : power consumption can be signifi- cantly reduced by running the cpu and the pe- ripherals at reduced clock speed using the cpu prescaler and ccu clock divider. wait for interrupt mode : the wait for in- terrupt (wfi) instruction suspends program exe- cution until an interrupt request is acknowledged. during wfi, the cpu clock is halted while the pe- ripheral and interrupt controller keep running at a frequency depending on the ccu programming. low power wait for interrupt mode : combining slow mode and wait for interrupt mode it is possible to reduce the power consump- tion by more than 80%. stop mode : when the stop is requested by executing the stop bit writing sequence (see dedicated section on wake-up management unit paragraph), and if nmi is kept low, the cpu and the peripherals stop operating. operations resume after a wake-up line is activated (16 wake-up lines plus nmi pin). see the rccu and wake-up man- agement unit paragraphs in the following for the details. the difference with the halt mode con- sists in the way the cpu exits this state: when the stop is executed, the status of the registers is re- corded, and when the system exits from the stop mode the cpu continues the execution with the same status, without a system reset. when the mcu enters stop mode the watchdog stops counting. after the mcu exits from stop mode, the watchdog resumes counting from where it left off. when the mcu exits from stop mode, the oscil- lator, which was sleeping too, requires about 5 ms to restart working properly (at a 4 mhz oscillator frequency). an internal counter is present to guar- antee that all operations after exiting stop mode, take place with the clock stabilised. the counter is active only when the oscillation has already taken place. this means that 1-2 ms must be added to take into account the first phase of the oscillator restart. halt mode : when executing the halt instruc- tion, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode. 9
30/398 st92f124/f150/f250 - device architecture 2 device architecture 2.1 core architecture the st9 core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9 family devices highly efficient, both for numerical calculation, data handling and with re- gard to communication with on-chip peripheral re- sources. 2.2 memory spaces there are two separate memory spaces: C the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. C a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 18 . a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 19 ): C 224 general purpose registers (group 0 to d, registers r0 to r223) C 6 system registers in the system group (group e, registers r224 to r239) C up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 20 . figure 18. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132 9
31/398 st92f124/f150/f250 - device architecture memory spaces (contd) figure 19. register groups figure 20. page pointer for group f mapping figure 21. addressing the register file f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234 register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers 9
32/398 st92f124/f150/f250 - device architecture memory spaces (contd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 21 ). group d registers can only be ad- dressed in working register mode. note that an upper case r is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form rx , where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case r is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 2.3.3 register pointing techniques, and illustrated in figure 22 and in figure 23 . system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 2.3 sys- tem registers. paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these regis- ters therefore depends on the peripherals which are present in the specific st9 family device. in other words, pages only exist if the relevant pe- ripheral is present. table 5. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0 9
33/398 st92f124/f150/f250 - device architecture 2.3 system registers the system registers are listed in table 6 . they are used to perform all the important system set- tings. their purpose is described in the following pages. refer to the chapter dealing with i/o for a description of the port[5:0] data registers. table 6. system registers (group e) 2.3.1 central interrupt control register please refer to the interrupt chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable . this bit is the global counter enable of the multi- function timers. the gcen bit is anded with the ce bit in the tcr register (only in devices featur- ing the mft multifunction timer) in order to enable the timers when both bits are set. this bit is set af- ter the reset cycle. note: if an mft is not included in the st9 device, then this bit has no effect. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bits 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) port1 data reg. r224 (e0h) port0 data reg. 70 gce n tlip tli ien iam cpl2 cpl1 cpl0 9
34/398 st92f124/f150/f250 - device architecture system registers (contd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h ) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in twos-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp 9
35/398 st92f124/f150/f250 - device architecture system registers (contd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the current st9 devices, the dp flag is only for compatibility with software developed for the first generation of st9 devices. with the single memory addressing space, its use is now redun- dant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form rxxx . 9
36/398 st92f124/f150/f250 - device architecture system registers (contd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bits 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bits 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 9
37/398 st92f124/f150/f250 - device architecture system registers (contd) figure 22. pointing to a single group of 16 registers figure 23. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & register pointer 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8 9
38/398 st92f124/f150/f250 - device architecture system registers (contd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh ) bits 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bits 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: C selection of internal or external system and user stack areas, C management of the clock frequency, C enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : crystal oscillator clock divided by 2 . this bit controls the divide-by-2 circuit operating on the crystal oscillator clock (clock1). 0: clock divided by 1 1: clock divided by 2 bits 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on breq pin (where available). note: disregard this bit if breq pin is not availa- ble. bit 0 = himp : high impedance enable . when a port is programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, ds, r/w) can be forced into the high impedance state. 0: external memory interface lines in normal state 1: high impedance state. 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp 9
39/398 st92f124/f150/f250 - device architecture note: setting the himp bit is recommended for noise reduction when only internal memory is used. if the memory access ports are declared as an ad- dress and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the bottom of the stacks which are f illed using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is pushed in and post-incremented when data is popped out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix u . to use a stack in- struction for a word, the suffix w is added. these suffixes may be combined. when bytes (or words) are popped out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is popped from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: C interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. C subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. C link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 6 . stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group. 9
40/398 st92f124/f150/f250 - device architecture system registers (contd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 24. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 25. external stack mode 70 usp15 usp14 usp13 usp12 usp11 usp10 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 register file stack pointer (low) points to: stack 70 ssp15 ssp14 ssp13 ssp12 ssp11 ssp10 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) & 9
41/398 st92f124/f150/f250 - device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9 provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map. 9
42/398 st92f124/f150/f250 - device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 7 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of three 6-bit registers (csr, isr, and dmasr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory ac- cesses during code execution (csr), interrupts service routines (isr or csr), and dma trans- fers (dmasr or isr). figure 26. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting) 9
43/398 st92f124/f150/f250 - device architecture 2.6 address space extension to manage 4 mbytes of addressing space, it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space if no dma is being performed. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 27 ). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction popw dpr0 is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 27. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m sb 14 lsb 9
44/398 st92f124/f150/f250 - device architecture address space extension (contd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address data memory space during a dma and program mem- ory space during any code execution (normal code and interrupt routines). three registers are used: csr, isr, and dmasr. the 6-bit contents of one of the registers csr, isr, or dmasr define one out of 64 memory seg- ments of 64 kbytes within the 4 mbytes address space. the register contents represent the 6 msbs of the memory address, whereas the 16 lsbs of the address (intra-segment address) are given by the virtual 16-bit address (see figure 28 ). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 26 . figure 28. addressing via csr, isr, and dmasr fetching program data memory fetching interrupt instruction accessed in dma instruction or dma access to program memory 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr dmasr 1 2 3 1 2 3 9
45/398 st92f124/f150/f250 - device architecture mmu registers (contd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bits 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bits 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bits 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bits 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0 _7 dpr0 _6 dpr0 _5 dpr0 _4 dpr0 _3 dpr0 _2 dpr0 _1 dpr0 _0 70 dpr1 _7 dpr1 _6 dpr1 _5 dpr1 _4 dpr1 _3 dpr1 _2 dpr1 _1 dpr1 _0 70 dpr2 _7 dpr2 _6 dpr2 _5 dpr2 _4 dpr2 _3 dpr2 _2 dpr2 _1 dpr2 _0 70 dpr3 _7 dpr3 _6 dpr3 _5 dpr3 _4 dpr3 _3 dpr3 _2 dpr3 _1 dpr3 _0 9
46/398 st92f124/f150/f250 - device architecture mmu registers (contd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bits 7:6 = reserved, keep in reset state. bits 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bits 7:6 = reserved, keep in reset state. bits 5:0 = isr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines and dma transfers (when the ps bit of the dapr register is reset). these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space in two cases: C whenever an interrupt occurs: isr points to the 64-kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. see also the interrupts chapter. C during dma transactions between the peripheral and memory when the ps bit of the dapr regis- ter is reset : isr points to the 64 k-byte memory segment that will be involved in the dma trans- action. 2.7.4 dmasr: dma segment register dma segment register (dmasr) r249 - read/write register page: 21 reset value: undefined bits 7:6 = reserved, keep in reset state. bits 5:0 = dmasr_[5:0] : these bits define the 64- kbyte memory segment (among 64) used when a dma transaction is performed between the periph- eral's data register and memory, with the ps bit of the dapr register set. these bits are used as the most significant address bits (a21-16). if the ps bit is reset, the isr register is used to extend the ad- dress. 70 0 0 csr_5 csr_4 csr_3 csr_2 csr_1 csr_0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0 70 00 dma sr_5 dma sr_4 dma sr_3 dma sr_2 dma sr_1 dma sr_0 9
47/398 st92f124/f150/f250 - device architecture mmu registers (contd) figure 29. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h dmasr isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 64k 16k 9
48/398 st92f124/f150/f250 - device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion. 2.8.3 dma depending on the ps bit in the dapr register (see dma chapter) dma uses either the isr or the dmasr for memory accesses: this guarantees that a dma will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. unlike interrupts, dma transactions cannot save/restore paging registers, so a dedicated segment register (dmasr) has been created. having only one register of this kind means that all dma accesses should be pro- grammed in one of the two following segments: the one pointed to by the isr (when the ps bit of the dapr register is reset), and the one refer- enced by the dmasr (when the ps bit is set). 9
49/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3 single voltage flash & e 3 tm (emulated eeprom) 3.1 introduction the flash circuitry contains one array divided in two main parts that can each be read independ- ently. the first part contains the main flash array for code storage, a reserved array (testflash) for system routines and a 128-byte area available as one time programmable memory (otp). the sec- ond part contains the two dedicated flash sectors used for eeprom hardware emulation. the write operations of the two parts are managed by an embedded program/erase controller. through a dedicated ram buffer the flash and the e 3 tm can be written in blocks of 16 bytes. figure 30. flash memory structure (example for 128k flash device) 230000h 010000h 004000h 002000h 000000h 228fffh 22c000h sector f3 64 kbytes sector f2 48 kbytes sector f1 8 kbytes sector f0 8 kbytes hardware emulated eeprom sectors 8 kbytes (reserved) emulated eeprom 1 kbyte testflash 8 kbytes program / erase controller ram buffer 16 bytes register interface address data 231f80h user otp and protection registers sense amplifiers sense amplifiers 220000h 2203ffh 9
50/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) figure 31. flash memory structure (example for 64k flash device) 230000h 010000h 004000h 002000h 000000h sector f3 16 kbytes sector f2 32 kbytes sector f1 8 kbytes sector f0 8 kbytes testflash 8 kbytes program / erase controller ram buffer 16 bytes register interface address data 231f80h user otp and protection registers sector f2 32 kbytes 00c000h sense amplifiers 228fffh 22c000h hardware emulated eeprom sectors 8 kbytes (reserved) emulated eeprom 1 kbyte sense amplifiers 220000h 2203ffh 013fffh 9
51/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3.2 functional description 3.2.1 structure the memory is composed of three parts: C a sector wih the system routines (testflash) and the user otp area C 4 main sectors for code C an emulated eeprom 124 bytes are available to the user as an otp ar- ea. the user can program these bytes, but cannot erase them. 3.2.2 eeprom emulation a hardware eeprom emulation is implemented using special flash sectors to emulate an eep- rom memory. this e 3 tm is directly addressed from 220000h to 2203ffh. (for more details on hardware eeprom emula- tion, see application note an1152) table 7. memory structure for 256k flash device table 8. memory structure for 128k flash device sector addresses max size testflash (tf) (reserved) 230000h to 231f7fh 8064 bytes otp area protection registers (reserved) 231f80h to 231ffbh 231ffch to 231fffh 124 bytes 4 bytes flash 0 (f0) 000000h to 001fffh 8 kbytes flash 1 (f1) 002000h to 003fffh 8 kbytes flash 2 (f2) 004000h to 00ffffh 48 kbytes flash 3 (f3) flash 4 (f4) flash 5 (f5) 010000h to 01ffffh 020000h to 02ffffh 030000h to 03ffffh 64 kbytes 64 kbytes 64 kbytes hardware emulated eeprom sectors (reserved) 228000h to 22cfffh 8 kbytes emulated eeprom 220000h to 2203ffh 1 kbyte sector addresses max size testflash (tf) (reserved) 230000h to 231f7fh 8064 bytes otp area protection registers (reserved) 231f80h to 231ffbh 231ffch to 231fffh 124 bytes 4 bytes flash 0 (f0) 000000h to 001fffh 8 kbytes flash 1 (f1) 002000h to 003fffh 8 kbytes flash 2 (f2) 004000h to 00ffffh 48 kbytes flash 3 (f3) 010000h to 01ffffh 64 kbytes hardware emulated eeprom sectors (reserved) 228000h to 22cfffh 8 kbytes emulated eeprom 220000h to 2203ffh 1 kbyte 9
52/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) functional description (contd) table 9. memory structure for 64k flash device sector addresses max size testflash (tf) (reserved) 230000h to 231f7fh 8064 bytes otp area protection registers (reserved) 231f80h to 231ffbh 231ffch to 231fffh 124 bytes 4 bytes flash 0 (f0) 000000h to 001fffh 8 kbytes flash 1 (f1) 002000h to 003fffh 8 kbytes flash 2 (f2) 004000h to 00bfffh 32 kbytes flash 3 (f3) 010000h to 013fffh 16 kbytes hardware emulated eeprom sectors (reserved) 228000h to 22cfffh 8 kbytes emulated eeprom 220000h to 2203ffh 1 kbyte 9
53/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) functional description (contd) 3.2.3 operation the memory has a register interface mapped in memory space (segment 22h). all operations are enabled through the fcr (flash control register), ecr ( e 3 tm control register). all operations on the flash must be executed from another memory (internal ram, e 3 tm , external memory). flash (including testflash) and e 3 tm are inde- pendent, this means that one can be read while the other is written. however simultaneous flash and e 3 tm write operations are forbidden. an interrupt can be generated at the end of a flash or an e 3 tm write operation: this interrupt is multiplexed with an external interrupt extintx (device dependent) to generate an interrupt intx. the status of a write operation inside the flash and the e 3 tm memories can be monitored through the fesr[1:0] registers. control and status registers are mapped in mem- ory (segment 22h), as shown in the following fig- ure. figure 32. control and status register map. in order to use the same data pointer register (dpr) to point both to the e 3 tm (220000h- 2203ffh) and to these control and status regis- ters, the flash and e 3 tm control registers are mapped not only at page 0x89 (224000h- 224003h) but also on page 0x88 (221000h- 221003h). if the reset pin is activated during a write opera- tion, the write operation is interrupted. in this case the user must repeat this last write operation fol- lowing power on or reset. if the internal supply volt- age drops below the v it- threshold, a reset se- quence is generated automatically by hardware. 3.2.4 e 3 tm update operation the update of the e 3 tm content can be made by pages of 16 consecutive bytes. the page update operation allows up to 16 bytes to be loaded into the ram buffer that replace the ones already con- tained in the specified address. each time a page update operation is executed in the e 3 tm , the ram buffer content is programmed in the next free block relative to the specified page (the ram buffer is previously automatically filled with old data for all the page addresses not select- ed for updating). if all the 4 blocks of the specified page in the current e 3 tm sector are full, the page content is copied to the complementary sector, that becomes the new current one. after that the specified page has been copied to the next free block, one erase phase is executed on the complementary sector, if the 4 erase phas- es have not yet been executed. when the selected page is copied to the complementary sector, the remaining 63 pages are also copied to the first block of the new sector; then the first erase phase is executed on the previous full sector. all this is executed in a hidden manner, and the end page update interrupt is generated only after the end of the complete operation. at reset the two status pages are read in order to detect which is the sector that is currently mapping the e 3 tm , and in which block each page is mapped. a system defined routine written in test- flash is executed at reset, so that any previously aborted write operation is restarted and complet- ed. 224000h 224001h register interface 224002h fcr ecr fesr0 fesr1 224003h 221000h 221001h 221002h 221003h / / / / 9
54/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) figure 33. hardware emulation flow emulation flow reset read status pages map e 3 tm in current sector write operation to complete ? complete write operation update status page ye s no wait for update commands page update command end page update interrupt (to core) program selected page from ram buffer in next free block copy all other pages into ram buffer; then program them in next free block 1/4 erase of complementary sector update status page new sector ? ye s no complementary sector erased ? ye s no 9
55/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3.3 register description 3.3.1 control registers flash control register (fcr) address: 224000h / 221000h- read/write reset value: 0000 0000 (00h) the flash control register is used to enable all the operations for the flash and the testflash memories. bit 7 = fwms: flash write mode start (read/ write). this bit must be set to start each write/erase oper- ation in flash memory. at the end of the write/ erase operation or during a sector erase suspend this bit is automatically reset. to resume a sus- pended sector erase operation, this bit must be set again. resetting this bit by software does not stop the current write operation. 0: no effect 1: start flash write bit 6 = fpage : flash page program (read/write) . this bit must be set to select the page program operation in flash memory. this bit is automatical- ly reset at the end of the page program operation. the page program operation allows to program 0s in place of 1s. from 1 to 16 bytes can be en- tered (in any order, no need for an ordered ad- dress sequence) before starting the execution by setting the fwms bit. all the addresses must be- long to the same page (only the 4 lsbs of address can change). data to be programmed and ad- dresses in which to program must be provided (through an ld instruction, for example). data contained in page addresses that are not entered are left unchanged. 0: deselect page program 1: select page program bit 5 = fchip: flash chip erase (read/write). this bit must be set to select the chip erase oper- ation in flash memory. this bit is automatically re- set at the end of the chip erase operation. the chip erase operation erases all the flash lo- cations to ffh. the operation is limited to flash code: sectors f0-f3 (or f0-f5 for the st92f250), testflash and e 3 tm excluded. the execution starts by setting the fwms bit. it is not necessary to pre-program the sectors to 00h, because this is done automatically. 0: deselect chip erase 1: select chip erase bit 4 = fbyte : flash byte program (read/write). this bit must be set to select the byte program op- eration in flash memory. this bit is automatically reset at the end of the byte program operation. the byte program operation allows 0s to be pro- grammed in place of 1s. data to be programmed and an address in which to program must be pro- vided (through an ld instruction, for example) be- fore starting execution by setting bit fwms. 0: deselect byte program 1: select byte program bit 3 = fsect: flash sector erase (read/write). this bit must be set to select the sector erase op- eration in flash memory. this bit is automatically reset at the end of the sector erase operation. the sector erase operation erases all the flash locations to ffh. from 1 to 6 sectors (f0-f5) can be simultaneously erased. these sectors can be entered before starting the execution by setting the fwms bit. an address located in the sector to erase must be provided (through an ld instruc- tion, for example), while the data to be provided is dont care. it is not necessary to pre-program the sectors to 00h, because this is done automatically. 0: deselect sector erase 1: select sector erase bit 2 = fsusp : flash sector erase suspend (read/write) . this bit must be set to suspend the current sector erase operation in flash memory in order to read data to or from program data to a sector not being erased. the fsusp bit must be reset (and fwms must be set again) to resume a suspended sector erase operation. the erase suspend operation resets the flash memory to normal read mode (automatically reset- ting bit fbusy) in a maximum time of 15 m s. 76543 210 fwms fpage fchip fbyte fsect fsusp prot fbusy 9
56/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) register description (contd) when in erase suspend the memory accepts only the following operations: read, erase resume and byte program. updating the e 3 tm memory is not possible during a flash erase suspend. 0: resume sector erase when fwms is set again. 1: suspend sector erase bit 1 = prot : set protection (read/write). this bit must be set to select the set protection op- eration. this bit is automatically reset at the end of the set protection operation. the set protection operation allows 0s in place of 1s to be programmed in the four non volatile protection registers. from 1 to 4 bytes can be en- tered (in any order, no need for an ordered ad- dress sequence) before starting the execution by setting the fwms bit. data to be programmed and addresses in which to program must be provided (through an ld instruction, for example). protec- tion contained in addresses that are not entered are left unchanged. 0: deselect protection 1: select protection bit 0 = fbusy : flash busy (read only). this bit is automatically set during page program, byte program, sector erase or set protection op- erations when the first address to be modified is latched in flash memory, or during chip erase op- eration when bit fwms is set. when this bit is set every read access to the flash memory will output invalid data (ffh equivalent to a nop instruction), while every write access to the flash memory will be ignored. at the end of the write operations or during a sector erase suspend this bit is automat- ically reset and the memory returns to read mode. after an erase resume this bit is automatically set again. the fbusy bit remains high for a maxi- mum of 10 m s after power-up and when exiting power-down mode, meaning that the flash mem- ory is not yet ready to be accessed. 0: flash not busy 1: flash busy e 3 tm control register (ecr) address: 224001h /221001h- read/write reset value: 000x x000 (xxh) the e 3 tm control register is used to enable all the operations for the e 3 tm memory. the ecr also contains two bits (wfis and feien) that are related to both flash and e 3 tm memories. bit 7 = ewms : e 3 tm write mode start . this bit must be set to start every write/erase oper- ation in the e 3 tm memory. at the end of the write/ erase operation this bit is automatically reset. re- setting by software this bit does not stop the cur- rent write operation. 0: no effect 1: start e 3 tm write bit 6 = epage : e 3 tm page update. this bit must be set to select the page update op- eration in e 3 tm memory. the page update opera- tion allows to write a new content: both 0s in place of 1s and 1s in place of 0s. from 1 to 16 bytes can be entered (in any order, no need for an ordered address sequence) before starting the ex- ecution by setting bit ewms. all the addresses must belong to the same page (only the 4 lsbs of address can change). data to be programmed and addresses in which to program must be provided (through an ld instruction, for example). data contained in page addresses that are not entered are left unchanged. this bit is automatically reset at the end of the page update operation. 0: deselect page update 1: select page update bit 5 = echip : e 3 tm chip erase. this bit must be set to select the chip erase oper- ation in the e 3 tm memory. the chip erase opera- tion allows to erase all the e 3 tm locations to ffh. the execution starts by setting bit ewms. this bit is automatically reset at the end of the chip erase operation. 0: deselect chip erase 1: select chip erase bit 4:3 = reserved. 76543210 ewms epage echip wfis feien ebusy 9
57/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) register description (contd) bit 2 = wfis : wait for interrupt status. if this bit is reset, the wfi instruction puts the flash macrocell in stand-by mode (immediate read possible, but higher consumption: 100 m a); if it is set, the wfi instruction puts the flash macro- cell in power-down mode (recovery time of 10 m s needed before reading, but lower consumption: 10 m a). the stand-by mode or the power-down mode will be entered only at the end of any current flash or e 3 tm write operation. in the same way following an halt or a stop in- struction, the memory enters power-down mode only after the completion of any current write oper- ation. 0: flash in stand-by mode on wfi 1: flash in power-down mode on wfi note: halt or stop mode can be exited without problems, but the user should take care when ex- iting wfi power down mode. if wfis is set, the user code must reset the xt_div16 bit in the r242 register (page 55) before executing the wfi instruction. when exiting wfi mode, this gives the flash enough time to wake up before the interrupt vector fetch. bit 1 = feien : flash & e 3 tm interrupt enable . this bit selects the source of interrupt channel intx between the external interrupt pin and the flash/ e 3 tm end of write interrupt. refer to the in- terrupt chapter for the channel number. 0: external interrupt enabled 1: flash & e 3 tm interrupt enabled bit 0 = ebusy: e 3 tm busy (read only). this bit is automatically set during a page update operation when the first address to be modified is latched in the e 3 tm memory, or during chip erase operation when bit ewms is set. at the end of the write operation or during a sector erase suspend this bit is automatically reset and the memory re- turns to read mode. when this bit is set every read access to the e 3 tm memory will output invalid data (ffh equivalent to a nop instruction), while every write access to the e 3 tm memory will be ignored. at the end of the write operation this bit is automat- ically reset and the memory returns to read mode. bit ebusy remains high for a maximum of 10ms after power-up and when exiting power-down mode, meaning that the e 3 tm memory is not yet ready to be accessed. 0: e 3 tm not busy 1: e 3 tm busy 3.3.2 status registers two status registers (fesr[1:0] are available to check the status of the current write operation in flash and e 3 tm memories. during a flash or an e 3 tm write operation any at- tempt to read the memory under modification will output invalid data (ffh equivalent to a nop in- struction). this means that the flash memory is not fetchable when a write operation is active: the write operation commands must be given from an- other memory ( e 3 tm , internal ram, or external memory). flash & e 3 tm status register 0 (fesr0) address: 224002h /221002h -read/write reset value: 0000 0000 (00h) bit 7 = feerr : flash or e 3 tm write error (read/ write). this bit is set by hardware when an error occurs during a flash or an e 3 tm write operation. it must be cleared by software. 0: write ok 1: flash or e 3 tm write error bit 6:0 = fess[6:0] . flash and e 3 tm sectors sta- tus bits (read only). these bits are set by hardware and give the status of the 7 flash and e 3 tm sectors. C fess6 = testflash and otp C fess5:4 = e 3 tm sectors for 128k and 64k flash devices: C fess3:0 = flash sectors (f3:0) for the st92f250 (256k): C fess3 gives the status of f5, f4 and f3 sectors: the status of all these three sectors are ored on this bit C fess2:0 = flash sectors (f2:0) 7 6543210 feerr fess6 fess5 fess4 fess3 fess2 fess1 fess0 9
58/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) register description (contd) the meaning of the fessx bit for sector x is given in table 10 . flash & e 3 tm status register 1 (fesr1) address: 224003h /221003h-read only reset value: 0000 0000 (00h) bit 7 = erer . erase error (read only). this bit is set by hardware when an erase error oc- curs during a flash or an e 3 tm write operation. this error is due to a real failure of a flash cell, that can no longer be erased. this kind of error is fatal and the sector where it occurred must be dis- carded. this bit is automatically cleared when bit feerr of the fesr0 register is cleared by soft- ware. 0: erase ok 1: erase error bit 6 = pger . program error (read only). this bit is automatically set when a program error occurs during a flash or an e 3 tm write operation. this error is due to a real failure of a flash cell, that can no longer be programmed. the byte where this error occurred must be discarded (if it was in the e 3 tm memory, the byte must be repro- grammed to ffh and then discarded, to avoid the error occurring again when that byte is internally moved). this bit is automatically cleared when bit feerr of the fesr0 register is cleared by soft- ware. 0: program ok 1: flash or e 3 tm programming error bit 5 = swer . swap or 1 over 0 error (read on- ly). this bit has two different meanings, depending on whether the current write operation is to flash or e 3 tm memory. in flash memory this bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the protec- tion bits). this error is not due to a failure of the flash cell, but only flags that the desired data has not been written. in the e 3 tm memory this bit is automatically set when a program error occurs during the swapping of the unselected pages to the new sector when the old sector is full (see an1152 for more details). this error is due to a real failure of a flash cell, that can no longer be programmed. when this er- ror is detected, the embedded algorithm automati- cally exits the page update operation at the end of the swap phase, without performing the erase phase 0 on the full sector. in this way the old data are kept, and through predefined routines in test- flash (find wrong pages = 230029h and find wrong bytes = 23002ch), the user can compare the old and the new data to find where the error oc- curred. once the error has been discovered the user must take to end the stopped erase phase 0 on the old sector (through another predefined routine in test- flash : complete swap = 23002fh). the byte where the error occurred must be reprogrammed to ffh and then discarded, to avoid the error oc- curring again when that byte is internally moved. this bit is automatically cleared when bit feerr of the fesr0 register is cleared by software. bit 4:0 = reserved. table 10. sector status bits feerr fbusy ebusy fsusp fessx=1 meaning 1- - write error in sector x 01 - write operation on-going in sec- tor x 001 sector erase suspended in sector x 000 dont care 76543210 erer pger swer 9
59/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3.4 write operation example each operation (both flash and e 3 tm ) is activated by a sequence of instructions like the following: or fcr, #opmask ;operation selection ld add1, #data1 ;1st add and data ld add2, #data2 ;2nd add and data .. ...., ...... ld addn, #datan ;nth add and data ;n range = (1 to 16) or fcr, #80h ;operation start the first instruction is used to select the desired operation by setting its corresponding selection bit in the control register (fcr for flash operations, ecr for e 3 tm operations). the load instructions are used to set the address- es (in the flash or in the e 3 tm memory space) and the data to be modified. the last instruction is used to start the write oper- ation, by setting the start bit (fwms for flash op- erations, ewms for e 3 tm operation) in the control register. once selected, but not yet started, one operation can be cancelled by resetting the operation selec- tion bit. any latched address and data will be reset. warning: during the flash page program or the e 3 tm page update operation it is forbidden to change the page address: only the last page address is ef- fectively kept and all programming will effect only that page. a summary of the available flash and e 3 tm write operations are shown in the following tables: table 11. flash write operations table 12. e 3 tm write operations operation selection bit addresses and data start bit typical duration byte program fbyte 1 byte fwms 10 m s page program fpage from 1 to 16 bytes fwms 160 m s (16 bytes) sector erase fsect from 1 to 4 sectors fwms 1.5 s (1 sector) sector erase suspend fsusp none none 15 m s chip erase fchip none fwms 3 s set protection prot from 1 to 4 bytes fwms 40 m s (4 bytes) operation selection bit addresses and data start bit typical duration page update epage from 1 to 16 bytes ewms 30 ms chip erase echip none ewms 70 ms 9
60/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3.5 protection strategy the protection bits are stored in the 4 locations from 231ffch to 231fffh (see figure 34 ). all the available protections are forced active dur- ing reset, then in the initialisation phase they are read from the testflash. the protections are stored in 2 non volatile regis- ters. other 2 non volatile registers can be used as a password to re-enable test modes once they have been disabled. the protections can be programmed using the set protection operation (see control registers para- graph), that can be executed from all the internal or external memories except the flash or test- flash itself. the testflash area (230000h to 231f7fh) is al- ways protected against write access. figure 34. protection register map 3.5.1 non volatile registers the 4 non volatile registers used to store the pro- tection bits for the different protection features are one time programmable by the user. access to these registers is controlled by the pro- tections related to the testflash. since the code to program the protection registers cannot be fetched by the flash or the testflash memories, this means that, once the apro or apbr bits in the nvapr register are programmed, it is no long- er possible to modify any of the protection bits. for this reason the nv password, if needed, must be set with the same set protection operation used to program these bits. for the same reason it is strongly advised to never program the wpbr bit in the nvwpr register, as this will prevent any fur- ther write access to the testflash, and conse- quently to the protection registers. non volatile access protection reg- ister (nvapr) address: 231ffch - read/write delivery value: 1111 1111 (ffh) bit 7 = reserved . bit 6 = apro : flash access protection. this bit, if programmed at 0, disables any access (read/write) to operands mapped inside the flash address space ( e 3 tm excluded), unless the current instruction is fetched from the testflash or from the flash itself. 0: rom protection on 1: rom protection off bit 5 = apbr : testflash access protection. this bit, if programmed at 0, disables any access (read/write) to operands mapped inside the test- flash, the otp and the protection registers, un- less the current instruction is fetched from the testflash or the otp area. 0: testflash protection on 1: testflash protection off bit 4 = apee : e 3 tm access protection. this bit, if programmed at 0, disables any access (read/write) to operands mapped inside the e 3 tm address space, unless the current instruction is fetched from the testflash or from the flash, or from the e 3 tm itself. 0: e 3 tm protection on 1: e 3 tm protection off bit 3 = apex : access protection from external memory. this bit, if programmed at 0, disables any access (read/write) to operands mapped inside the ad- dress space of one of the internal memories (test- flash, flash, e 3 tm , ram), if the current instruction is fetched from an external memory. 0: protection from external memory on 1: protection from external memory off nvapr nvwpr 231ffch 231ffdh 231ffeh nvpwd0 nvpwd1 231fffh 76543210 1 apro apbr apee apex pwt2 pwt1 pwt0 9
61/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) protection strategy (contd) bit 2:0 = pwt[2:0]: password attempt 2-0. if the tmdis bit in the nvwpr register (231ffdh) is programmed to 0, every time a set protection operation is executed with program addresses equal to nvpwd1-0 (231ffe-fh), the two provid- ed program data are compared with the nvpwd1-0 content; if there is not a match one of pwt2-0 bits is automatically programmed to 0: when these three bits are all programmed to 0 the test modes are disabled forever. in order to inten- tionally disable test modes forever, it is sufficient to set a random password and then to make 3 wrong attempts to enter it. non volatile write protection regis- ter (nvwpr) address: 231ffdh - read/write delivery value: 1111 1111 (ffh) bit 7 = tmdis : test mode disable (read only). this bit, if set to 1, allows to bypass all the protec- tions in test and epb modes. if programmed to 0, on the contrary, all the protections remain active also in test mode. the only way to enable the test modes if this bit is programmed to 0, is to execute the set protection operation with program ad- dresses equal to nvpwd1-0 (231fff-eh) and program data matching with the content of nvpwd1-0. this bit is read only: it is automatically programmed to 0 when nvpwd1-0 are written for the first time. 0: test mode disabled 1: test mode enabled bit 6 = pwok : password ok (read only). if the tmdis bit is programmed to 0, when the set protection operation is executed with program ad- dresses equal to nvpwd[1:0] and program data matching with nvpwd[1:0] content, the pwok bit is automatically programmed to 0. when this bit is programmed to 0 tmdis protection is bypassed and the test and epb modes are enabled. 0: password ok 1: password not ok bit 5 = wpbr: testflash write protection . this bit, if programmed at 0, disables any write ac- cess to the testflash, the otp and the protection registers. this protection cannot be temporarily disabled. 0: testflash write protection on 1: testflash write protection off note: it is strongly advised to never program the wpbr bit in the nvwpr register, as this will pre- vent any further write access to the protection reg- isters. bit 4 = wpee : e 3 tm write protection . this bit, if programmed to 0, disables any write ac- cess to the e 3 tm address space. this protection can be temporary disabled by executing the set protection operation and writing 1 into this bit. to restore the protection it needs to reset the micro or to execute another set protection operation and write 0 to this bit. 0: e 3 tm write protection on 1: e 3 tm write protection off bit 3 = wprs3: flash sectors 5-3 write protec- tion. this bit, if programmed to 0, disables any write ac- cess to the flash sector 3 (and sectors 4 and 5 when available) address space(s). this protection can be temporary disabled by executing the set protection operation and writing 1 into this bit. to restore the protection it needs to reset the micro or to execute another set protection operation and write 0 into this bit. 0: flash s ectors 5-3 write protection on 1: flash s ectors 5-3 write protection off bit 2:0 = wprs[2:0]: flash sectors 2-0 write protection. these bits, if programmed to 0, disable any write access to the 3 flash sectors address spaces. these protections can be temporary disabled by executing the set protection operation and writing 1 into these bits. to restore the protection it needs to reset the micro or to execute another set pro- tection operation and write 0 into these bits. 0: flash s ectors 2-0 write protection on 1: flash s ectors 2-0 write protection off 76543210 tmdis pwok wpbr wpee wprs3 wprs2 wprs1 wprs0 9
62/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) protection strategy (contd) non volatile password (nvpwd1-0) address: 231fff-231ffeh - write only delivery value: 1111 1111 (ffh) bit 7:0 = pwd[7:0]: password bits 7:0 (write on- ly). these bits must be programmed with the non vol- atile password that must be provided with the set protection operation to disable (first write access) or to reenable (second write access) the test and epb modes. the first write access fixes the pass- word value and resets the tmdis bit of nvwpr (231ffdh). the second write access, with pro- gram data matching with nvpwd[1:0] content, re- sets the pwok bit of nvwpr. these two registers can be accessed only in write mode (a read access returns ffh). 3.5.2 temporary unprotection on user request the memory can be configured so as to allow the temporary unprotection also of all access protections bits of nvapr (write protection bits of nvwpr are always temporarily unprotecta- ble). bit apex can be temporarily disabled by execut- ing the set protection operation and writing 1 into this bit, but only if this write instruction is executed from an internal memory (flash and test flash ex- cluded). bit apee can be temporarily disabled by execut- ing the set protection operation and writing 1 into this bit, but only if this write instruction is executed from the memory itself to unprotect ( e 3 tm ). bits apro and apbr can be temporarily disabled through a direct write at nvapr location, by over- writing at 1 these bits, but only if this write instruc- tion is executed from the memory itself to unpro- tect. to restore the access protection bits it needs to re- set the micro or to execute a set protection opera- tion and write 0 into the desired bits. when an internal memory (flash, testflash or e 3 tm ) is protected in access, also the data access through a dma of a peripheral is forbidden (it re- turns ffh). to read data in dma mode from a pro- tected memory, first it is necessary to temporarily unprotect that memory. the temporary unprotection allows also to update a protected code. 76543210 pwd7 pwd6 pwd5 pwd4 pwd3 pwd2 pwd1 pwd0 9
63/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) 3.6 flash in-system programming the flash memory can be programmed in-system through a serial interface (sci0). exiting from reset, the st9 executes the initializa- tion from the testflash code (written in test- flash), where it checks the value of the sout0 pin. if it is at 0, this means that the user wishes to update the flash code, otherwise normal execu- tion continues. in this second case, the testflash code reads the reset vector. if the flash is virgin (read content is always ffh), the reset vector contains ffffh. this will repre- sent the last location of segment 0h, and it is inter- preted by the testflash code as a flag indicating that the flash memory is virgin and needs to be programmed. if the value 1 is detected on the sout0 pin and the flash is virgin, a halt instruc- tion is executed, waiting for a hardware reset. 3.6.1 code update routine the testflash code update routine is called auto- matically if the sout0 pin is held low during pow- er-on. the code update routine performs the following operations: n enables the sci0 peripheral in synchronous mode n transmits a synchronization datum (25h); n waits for an address match (23h) with a timeout of 10ms (@ f osc 4 mhz); n if the match is not received before the timeout, the execution returns to the power-on routine; n if the match is received, the sci0 transmits a new datum (21h) to tell the external device that it is ready to receive the data to be loaded in ram (that represents the code of the in-system programming routine); n receives two data representing the number of bytes to be loaded (max. 4 kbytes); n receives the specified number of bytes (each one preceded by the transmission of a ready to receive character: (21h) and writes them in internal ram starting from address 200010h. the first 4 words should be the interrupt vectors of the 4 possible sci interrupts, to be used by the in-system programming routine; n transmits a last datum (21h) as a request for end of communications; n receives the end of communication confirmation datum (any byte other than 25h); n resets all the unused ram locations to ffh; n calls address 200018h in internal ram; n after completion of the in-system programming routine, an halt instruction is executed and an hardware reset is needed. the code update routine initializes the sci0 pe- ripheral as shown in the following table: table 13. sci0 registers (page 24) initialization in addition, the code update routine remaps the interrupts in the testflash (isr = 23h), and config- ures i/o ports p5.3 (sout0) and and p5.4 (clkout0) as alternate functions. note: four interrupt routines are used by the code update routine: sci receiver error interrupt rou- tine (vector in 0010h), sci address match interrupt routine (vector in 0012h), sci receiver data ready interrupt routine (vector in 0014h) and sci transmitter buffer empty interrupt routine (vector in 0016h). register value notes ivr - r244 10h vector table in 0010h acr - r245 23h address match is 23h idpr - r249 00h sci interrupt priority is 0 chcr - r250 83h 8 data bits ccr - r251 e8h rec. clock: ext rxclk0 trx clock: int clkout0 brghr - r252 00h brglr - r253 04h baud rate divider is 4 sicr - r254 83h synchronous mode socr - r255 01h 9
64/398 st92f124/f150/f250 - single voltage flash & e3 tm (emulated eeprom) figure 35. flash in-system programming. testflash code start initialisation enable serial interface jump to flash main code in-system prog routine flash virgin ? erase sectors ye s no load 1st table of data in ram through s.i. prog 1st table of data from ram in flash load 2nd table of data in ram through sci inc. address last address ? ret ye s no code update routine enable dma load in-system prog routine in internal ram through sci. call in-system prog routine halt address match interrupt (from sci) user test internal ram (user code example) sout0 = 0 ? ye s no wfi flash 9
65/398 st92f124/f150/f250 - register and memory map 4 register and memory map 4.1 introduction the st92f124/f150/f250 register map, memory map and peripheral options are documented in this section. use this reference information to sup- plement the functional descriptions given else- where in this document. 4.2 memory configuration the program memory space of the st92f124/ f150/f250 up to 256k bytes of directly addressa- ble on-chip memory, is fully available to the user. 4.2.1 reset vector location the user power on reset vector must be stored in the first two physical bytes of memory, 000000h and 000001h. 4.2.2 location of vector for external watchdog refresh if an external watchdog is used, it must be re- freshed during testflash execution by a user writ- ten routine. this routine has to be located in flash memory, the address where the routine starts has to be written in 000006h (one word) while the seg- ment where the routine is located has to be written in 000009h (one byte). this routine is called at least once every time that the testflash executes an e 3 tm write operation. if the write operation has a long duration, the user routine is called with a rate fixed by location 000008h with an internal clock frequency of 2 mhz, location 000008h fixes the number of milli- seconds to wait between two calls of the user rou- tine. table 14. user routine parameters if location 000006h to 000007h is virgin (ffffh), the user routine is not called. location size description 000006h to 000007h 2 bytes user routine address 000008h 1 byte ms rate at 2 mhz. 000009h 1 byte user routine segment 9
66/398 st92f124/f150/f250 - register and memory map figure 36. st92f150/f250 external memory map (reserved for external memory external memory 250000h 3fffffh lower memory (usually external rom/flash upper memory (usually external ram starting starting in segment 4h) in segment 24h) 1fffffh 050000h segments 0h to 3h (256kbytes) internal memory) (reserved for segments 20h to 23h (256kbytes) internal memory) (1.8 mbytes) (1.8 mbytes) 040000h 04ffffh 04c000h 04bfffh 048000h 047fffh 044000h 043fffh page 10h - 16 kbytes page 11h - 16 kbytes page 12h - 16 kbytes page 13h - 16 kbytes segment 4h 64 kbytes 240000h 24ffffh 24c000h 24bfffh 248000h 247fffh 244000h 243fffh page 90h - 16 kbytes page 91h - 16 kbytes page 92h - 16 kbytes page 93h - 16 kbytes segment 24h 64 kbytes 9
67/398 st92f124/f150/f250 - register and memory map figure 37. st92f124/f150/f250 testflash and e 3 tm memory map testflash - 8 kbytes segment 23h 64 kbytes 230000h 23ffffh 23c000h 23bfffh 238000h 237fffh 234000h 233fffh page 8ch - 16 kbytes page 8dh - 16 kbytes page 8eh - 16 kbytes page 8fh - 16 kbytes 230000h 231fffh 8 kbytes 231f80h 231fffh flash otp - 128 bytes 231ffch 231fffh flash otp protection registers - 4 bytes 128 bytes 4 bytes emulated eeprom - 1 kbyte segment 22h 64 kbytes 220000h 22ffffh 22c000h 22bfffh 228000h 227fffh 224000h 223fffh page 88h - 16 kbytes page 89h- 16 kbytes page 8ah - 16 kbytes page 8bh - 16 kbytes 220000h 2203ffh 1 kbyte not available flash and e 3 tm 224000h/221003h 224003h/221000h mapped in both locations control registers - 4 bytes 9
68/398 st92f124/f150/f250 - register and memory map figure 38. st92f124/f150 internal memory map segment 1h 64 kbytes flash - 128 kbytes segment 0h 64 kbytes 01ffffh 01c000h 01bfffh 018000h 017fffh 014000h 010000h 013fffh 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 7h - 16 kbytes page 0h - 16 kbytes page 1h - 16 kbytes page 2h - 16 kbytes page 3h - 16 kbytes page 4h - 16 kbytes page 5h - 16 kbytes page 6h - 16 kbytes sector f0 8 kbytes not available sector f1 8 kbytes sector f2 48 kbytes sector f3 * 64 kbytes segment 3h 64 kbytes flash - 128 kbytes segment 2h 64 kbytes 03ffffh 03c000h 03bfffh 038000h 037fffh 034000h 030000h 033fffh 02ffffh 02c000h 02bfffh 028000h 027fffh 024000h 020000h 023fffh page fh - 16 kbytes page 8h- 16 kbytes page 9h - 16 kbytes page ah - 16 kbytes page bh - 16 kbytes page ch - 16 kbytes page dh- 16 kbytes page eh - 16 kbytes reserved area- 128 kbytes ram segment 20h 64 kbytes 200000h 20ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80h - 16 kbytes page 81h - 16 kbytes page 82h - 16 kbytes page 83h - 16 kbytes 200000h 2017ffh 200fffh 4 kbytes 6 kbytes 2 kbytes 2007ffh * available on st92f150 versions only. reserved area on st92f124 version . 9
69/398 st92f124/f150/f250 - register and memory map figure 39. st92f250 internal memory map segment 1h 64 kbytes flash - 256kbytes segment 0h 64 kbytes 01ffffh 01c000h 01bfffh 018000h 017fffh 014000h 010000h 013fffh 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 7h - 16 kbytes page 0h - 16 kbytes page 1h - 16 kbytes page 2h - 16 kbytes page 3h - 16 kbytes page 4h - 16 kbytes page 5h - 16 kbytes page 6h - 16 kbytes sector f0 8 kbytes not available sector f1 8 kbytes sector f2 48 kbytes sector f3 64 kbytes segment 3h 64 kbytes 03ffffh 03c000h 03bfffh 038000h 037fffh 034000h 030000h 033fffh 02ffffh 02c000h 02bfffh 028000h 027fffh 024000h 020000h 023fffh page fh - 16 kbytes page 8h- 16 kbytes page 9h - 16 kbytes page ah - 16 kbytes page bh - 16 kbytes page ch - 16 kbytes page dh- 16 kbytes page eh - 16 kbytes ram segment 20h 64 kbytes 200000h 20ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80h - 16 kbytes page 81h - 16 kbytes page 82h - 16 kbytes page 83h - 16 kbytes 200000h 201fffh 8kbytes sector f5 64 kbytes segment 2h 64 kbytes sector f4 64 kbytes 9
70/398 st92f124/f150/f250 - register and memory map 4.3 st92f124/f150/f250 register map table 16 contains the map of the group f periph- eral pages. the common registers used by each peripheral are listed in table 15 . be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. C in particular, double-check that any registers with undefined reset values have been correct- ly initialized. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. table 15. common registers function or peripheral common registers sci, mft cicr + nicr + dma registers + i/o port registers adc cicr + nicr + i/o port registers spi, wdt, stim cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder 9
71/398 st92f124/f150/f250 - register and memory map table 16. group f pages register map resources available on the st92f124/f150/f250 devices: reg. page 023789101120212223242628293637383940 r255 res. res port 7 res. mft1 res. mft0 res. i2c_0 mmu i2c_1 * jblpd * sci-m sci-a * eft0 * eft1 * can_1* can_1* can_1* can_1* can_1* r254 port 3 r253 r252 wcr r251 wdt res port 6 r250 port 2 r249 r248 mft0 r247 int res. res. mft1 r246 port 1 port 5 r245 r244 r243 res. res. spi mft0 stim r242 port 0 port 4 r241 res. r240 9
72/398 st92f124/f150/f250 - register and memory map : * available on some devices only reg. page 41 42 43 48 49 50 51 52 53 54 55 57 60 61 62 63 r255 can_1* can_1* port 9* can_0* can_0* can_0* can_0* can_0* can_0* can_0* res. wuimu standard interrupt channels ad10 ad10 ad10 r254 r253 r252 r251 port 8* r250 r249 r248 res. r247 res. r246 rccu r245 r244 res r243 r242 r241 r240 9
73/398 st92f124/f150/f250 - register and memory map table 17. detailed register map page (dec) block reg. no. register name description reset value hex. doc. page n/a core r230 cicr central interrupt control register 87 33 r231 flagr flag register 00 34 r232 rp0 pointer 0 register xx 36 r233 rp1 pointer 1 register xx 36 r234 ppr page pointer register xx 38 r235 moder mode register e0 38 r236 usphr user stack pointer high register xx 40 r237 usplr user stack pointer low register xx 40 r238 ssphr system stack pointer high reg. xx 40 r239 ssplr system stack pointer low reg. xx 40 i/o port 0:5 r224 p0dr port 0 data register ff 147 r225 p1dr port 1 data register ff r226 p2dr port 2 data register ff r227 p3dr port 3 data register 1111 111x r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff 0 int r242 eitr external interrupt trigger register 00 102 r243 eipr external interrupt pending reg. 00 103 r244 eimr external interrupt mask-bit reg. 00 103 r245 eiplr external interrupt priority level reg. ff 103 r246 eivr external interrupt vector register x6 159 r247 nicr nested interrupt control 00 104 wdt r248 wdthr watchdog timer high register ff 158 r249 wdtlr watchdog timer low register ff 158 r250 wdtpr watchdog timer prescaler reg. ff 158 r251 wdtcr watchdog timer control register 12 158 r252 wcr wait control register 7f 159 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 147 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 1 r244 p1c0 port 1 configuration register 0 00 r245 p1c1 port 1 configuration register 1 00 r246 p1c2 port 1 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 ff r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 i/o port 3 r252 p3c0 port 3 configuration register 0 1111 111x r253 p3c1 port 3 configuration register 1 0000 000x r254 p3c2 port 3 configuration register 2 0000 000x 9
74/398 st92f124/f150/f250 - register and memory map 3 i/o port 4 r240 p4c0 port 4 configuration register 0 fd 147 r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 ff r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 i/o port 6 r248 p6c0 port 6 configuration register 0 xx11 1111 r249 p6c1 port 6 configuration register 1 xx00 0000 r250 p6c2 port 6 configuration register 2 xx00 0000 r251 p6dr port 6 data register xx11 1111 i/o port 7 r252 p7c0 port 7 configuration register 0 ff r253 p7c1 port 7 configuration register 1 00 r254 p7c2 port 7 configuration register 2 00 r255 p7dr port 7 data register ff 7 spi r240 spdr0 spi data register 00 257 r241 spcr0 spi control register 00 257 r242 spsr0 spi status register 00 258 r243 sppr0 spi prescaler register 00 258 page (dec) block reg. no. register name description reset value hex. doc. page 9
75/398 st92f124/f150/f250 - register and memory map 8 mft1 r240 reg0hr1 capture load register 0 high xx 199 r241 reg0lr1 capture load register 0 low xx 199 r242 reg1hr1 capture load register 1 high xx 199 r243 reg1lr1 capture load register 1 low xx 199 r244 cmp0hr1 compare 0 register high 00 199 r245 cmp0lr1 compare 0 register low 00 199 r246 cmp1hr1 compare 1 register high 00 199 r247 cmp1lr1 compare 1 register low 00 199 r248 tcr1 timer control register 00 200 r249 tmr1 timer mode register 00 201 r250 t_icr1 external input control register 00 202 r251 prsr1 prescaler register 00 202 r252 oacr1 output a control register 00 203 r253 obcr1 output b control register 00 204 r254 t_flagr1 flags register 00 204 r255 idmr1 interrupt/dma mask register 00 206 9 r244 dcpr1 dma counter pointer register xx 199 r245 dapr1 dma address pointer register xx 199 r246 t_ivr1 interrupt vector register xx 199 r247 idcr1 interrupt/dma control register c7 199 mft0,1 r248 iocr i/o connection register fc 208 mft0 r240 dcpr0 dma counter pointer register xx 206 r241 dapr0 dma address pointer register xx 207 r242 t_ivr0 interrupt vector register xx 207 r243 idcr0 interrupt/dma control register c7 208 10 r240 reg0hr0 capture load register 0 high xx 199 r241 reg0lr0 capture load register 0 low xx 199 r242 reg1hr0 capture load register 1 high xx 199 r243 reg1lr0 capture load register 1 low xx 199 r244 cmp0hr0 compare 0 register high 00 199 r245 cmp0lr0 compare 0 register low 00 199 r246 cmp1hr0 compare 1 register high 00 199 r247 cmp1lr0 compare 1 register low 00 199 r248 tcr0 timer control register 00 200 r249 tmr0 timer mode register 00 201 r250 t_icr0 external input control register 00 202 r251 prsr0 prescaler register 00 202 r252 oacr0 output a control register 00 203 r253 obcr0 output b control register 00 204 r254 t_flagr0 flags register 00 204 r255 idmr0 interrupt/dma mask register 00 206 page (dec) block reg. no. register name description reset value hex. doc. page 9
76/398 st92f124/f150/f250 - register and memory map 11 stim r240 sth counter high byte register ff 163 r241 stl counter low byte register ff 163 r242 stp standard timer prescaler register ff 163 r243 stc standard timer control register 14 163 20 i2c_0 r240 i2dccr i 2 c control register 00 270 r241 i2csr1 i 2 c status register 1 00 271 r242 i2csr2 i 2 c status register 2 00 273 r243 i2cccr i 2 c clock control register 00 274 r244 i2coar1 i 2 c own address register 1 00 274 r245 i2coar2 i 2 c own address register 2 00 275 r246 i2cdr i 2 c data register 00 275 r247 i2cadr i 2 c general call address a0 275 r248 i2cisr i 2 c interrupt status register xx 276 r249 i2civr i 2 c interrupt vector register xx 277 r250 i2crdap receiver dma source addr. pointer xx 277 r251 i2crdc receiver dma transaction counter xx 277 r252 i2ctdap transmitter dma source addr. pointer xx 278 r253 i2ctdc transmitter dma transaction counter xx 278 r254 i2ceccr extended clock control register 00 278 r255 i2cimr i 2 c interrupt mask register x0 279 21 mmu r240 dpr0 data page register 0 xx 45 r241 dpr1 data page register 1 xx 45 r242 dpr2 data page register 2 xx 45 r243 dpr3 data page register 3 xx 45 r244 csr code segment register 00 46 r248 isr interrupt segment register xx 46 r249 dmasr dma segment register xx 46 extmi r245 emr1 external memory register 1 80 144 r246 emr2 external memory register 2 1f 145 page (dec) block reg. no. register name description reset value hex. doc. page 9
77/398 st92f124/f150/f250 - register and memory map 22 i2c_1* r240 i2dccr i 2 c control register 00 270 r241 i2csr1 i 2 c status register 1 00 271 r242 i2csr2 i 2 c status register 2 00 273 r243 i2cccr i 2 c clock control register 00 274 r244 i2coar1 i 2 c own address register 1 00 274 r245 i2coar2 i 2 c own address register 2 00 275 r246 i2cdr i 2 c data register 00 275 r247 i2cadr i 2 c general call address a0 275 r248 i2cisr i 2 c interrupt status register xx 276 r249 i2civr i 2 c interrupt vector register xx 277 r250 i2crdap receiver dma source addr. pointer xx 277 r251 i2crdc receiver dma transaction counter xx 277 r252 i2ctdap transmitter dma source addr. pointer xx 278 r253 i2ctdc transmitter dma transaction counter xx 278 r254 i2ceccr extended clock control register 00 278 r255 i2cimr i 2 c interrupt mask register x0 279 23 jblpd* r240 status status register 40 302 r241 txdata transmit data register xx 303 r242 rxdata receive data register xx 304 r243 txop transmit opcode register 00 304 r244 clksel system frequency selection register 00 309 r245 control control register 40 309 r246 paddr physical address register xx 310 r247 error error register 00 311 r248 ivr interrupt vector register xx 313 r249 prlr priority level register 10 313 r250 imr interrupt mask register 00 313 r251 options options and register group selection 00 315 r252 creg0 current register 0 xx 317 r253 creg1 current register 1 xx 317 r254 creg2 current register 2 xx 317 r255 creg3 current register 4 xx 317 page (dec) block reg. no. register name description reset value hex. doc. page 9
78/398 st92f124/f150/f250 - register and memory map 24 sci-m r240 rdcpr0 receiver dma transaction counter pointer xx 224 r241 rdapr0 receiver dma source address pointer xx 224 r242 tdcpr0 transmitter dma transaction counter pointer xx 224 r243 tdapr0 transmitter dma destination address pointer xx 224 r244 s_ivr0 interrupt vector register xx 226 r245 acr0 address/data compare register xx 226 r246 imr0 interrupt mask register x0 226 r247 s_isr0 interrupt status register xx 226 r248 rxbr0 receive buffer register xx 228 r248 txbr0 transmitter buffer register xx 228 r249 idpr0 interrupt/dma priority register xx 229 r250 chcr0 character configuration register xx 230 r251 ccr0 clock configuration register 00 231 r252 brghr0 baud rate generator high reg. xx 232 r253 brglr0 baud rate generator low register xx 232 r254 sicr0 synchronous input control 03 232 r255 socr0 synchronous output control 01 233 26 sci-a* r240 scisr sci status register c0 242 r241 scidr sci data register xx 245 r242 scibrr sci baud rate register xx 245 r243 scicr1 sci control register 1 xx 243 r244 scicr2 sci control register 2 00 244 r245 scierpr sci extended receive prescaler register 00 246 r246 scietpr sci extended transmit prescaler register 00 246 28 eft0* r240 ic1hr0 input capture 1 high register xx 178 r241 ic1lr0 input capture 1 low register xx 178 r242 ic2hr0 input capture 2 high register xx 178 r243 ic2lr0 input capture 2 low register xx 178 r244 chr0 counter high register ff 179 r245 clr0 counter low register fc 179 r246 achr0 alternate counter high register ff 179 r247 aclr0 alternate counter low register fc 179 r248 oc1hr0 output compare 1 high register 80 180 r249 oc1lr0 output compare 1 low register 00 180 r250 oc2hr0 output compare 2 high register 80 180 r251 oc2lr0 output compare 2 low register 00 180 r252 cr1_0 control register 1 00 182 r253 cr2_0 control register 2 00 182 r254 sr0 status register 00 182 r255 cr3_0 control register 3 00 182 page (dec) block reg. no. register name description reset value hex. doc. page 9
79/398 st92f124/f150/f250 - register and memory map 29 eft1* r240 ic1hr1 input capture 1 high register xx 178 r241 ic1lr1 input capture 1 low register xx 178 r242 ic2hr1 input capture 2 high register xx 178 r243 ic2lr1 input capture 2 low register xx 178 r244 chr1 counter high register ff 179 r245 clr1 counter low register fc 179 r246 achr1 alternate counter high register ff 179 r247 aclr1 alternate counter low register fc 179 r248 oc1hr1 output compare 1 high register 80 180 r249 oc1lr1 output compare 1 low register 00 180 r250 oc2hr1 output compare 2 high register 80 180 r251 oc2lr1 output compare 2 low register 00 180 r252 cr1_1 control register 1 00 182 r253 cr2_1 control register 2 00 182 r254 sr1 status register 00 182 r255 cr3_1 control register 3 00 182 36 can1* control/ status r240 cmcr can master control register 02 340 r241 cmsr can master status register 02 341 r242 ctsr can transmit control register 00 341 r243 ctpr can transmit priority register 00 342 r244 crfr0 can receive fifo register 0 00 343 r245 crfr1 can receive fifo register 1 00 343 r246 cier can interrupt enable register 00 343 r247 cesr can error status register 00 344 r248 ceier can error interrupt enable register 00 344 r249 tecr transmit error counter register 00 345 r250 recr receive error counter register 00 345 r251 cdgr can diagnosis register 00 345 r252 cbtr0 can bit timing register 0 00 346 r253 cbtr1 can bit timing register 1 23 346 r255 cfpsr filter page select register 00 346 page (dec) block reg. no. register name description reset value hex. doc. page 9
80/398 st92f124/f150/f250 - register and memory map 37 can1* receive fifo 0 r240 mfmi mailbox filter match index 00 348 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 38 can1* receive fifo 1 r240 mfmi mailbox filter match index 00 348 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 page (dec) block reg. no. register name description reset value hex. doc. page 9
81/398 st92f124/f150/f250 - register and memory map 39 can1 * tx mailbox 0 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 40 can1 * tx mailbox 1 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 page (dec) block reg. no. register name description reset value hex. doc. page 9
82/398 st92f124/f150/f250 - register and memory map 41 can1 * tx mailbox 2 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register x0 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 42 can1 * filters see page mapping for can 0 / can 1 on page 354 filter configuration acceptance filters 7:0 (5 register pages) 43 i/o port 8 * r248 p8c0 port 8 configuration register 0 03 147 r249 p8c1 port 8 configuration register 1 00 r250 p8c2 port 8 configuration register 2 00 r251 p8dr port 8 data register ff i/o port 9 * r252 p9c0 port 9 configuration register 0 00 r253 p9c1 port 9 configuration register 1 00 r254 p9c2 port 9 configuration register 2 00 r255 p9dr port 9 data register ff 48 can0* control/ status r240 cmcr can master control register 02 340 r241 cmsr can master status register 02 341 r242 ctsr can transmit control register 00 341 r243 ctpr can transmit priority register 00 342 r244 crfr0 can receive fifo register 0 00 343 r245 crfr1 can receive fifo register 1 00 343 r246 cier can interrupt enable register 00 343 r247 cesr can error status register 00 344 r248 ceier can error interrupt enable register 00 344 r249 tecr transmit error counter register 00 345 r250 recr receive error counter register 00 345 r251 cdgr can diagnosis register 00 345 r252 cbtr0 can bit timing register 0 00 346 r253 cbtr1 can bit timing register 1 23 346 r255 cfpsr filter page select register 00 346 page (dec) block reg. no. register name description reset value hex. doc. page 9
83/398 st92f124/f150/f250 - register and memory map 49 can0* receive fifo 0 r240 mfmi mailbox filter match index 00 348 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 50 can0* receive fifo 1 r240 mfmi mailbox filter match index 00 348 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 page (dec) block reg. no. register name description reset value hex. doc. page 9
84/398 st92f124/f150/f250 - register and memory map 51 can0* tx mailbox 0 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 52 can0* tx mailbox 1 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 page (dec) block reg. no. register name description reset value hex. doc. page 9
85/398 st92f124/f150/f250 - register and memory map 53 can0* tx mailbox 2 r240 mcsr mailbox control status register 00 347 r241 mdlc mailbox data length control register xx 349 r242 midr0 mailbox identifier register 0 xx 348 r243 midr1 mailbox identifier register 1 xx 348 r244 midr2 mailbox identifier register 2 xx 348 r245 midr3 mailbox identifier register 3 xx 348 r246 mdar0 mailbox data register 0 xx 349 r247 mdar1 mailbox data register 1 xx 349 r248 mdar2 mailbox data register 2 xx 349 r249 mdar3 mailbox data register 3 xx 349 r250 mdar4 mailbox data register 4 xx 349 r251 mdar5 mailbox data register 5 xx 349 r252 mdar6 mailbox data register 6 xx 349 r253 mdar7 mailbox data register 7 xx 349 r254 mtslr mailbox time stamp low register xx 349 r255 mtshr mailbox time stamp high register xx 349 54 can0* filters see page mapping for can 0 / can 1 on page 354. filter configuration acceptance filters 7:0 (5 register pages) 55 rccu r240 clkctl clock control register 00 130 r241 reserved r242 clk_flag clock flag register 64,48, 28 or 08 131 r246 pllconf pll configuration register xx 131 57 wuimu r249 wuctrl wake-up control register 00 114 r250 wumrh wake-up mask register high 00 115 r251 wumrl wake-up mask register low 00 115 r252 wutrh wake-up trigger register high 00 116 r253 wutrl wake-up trigger register low 00 116 r254 wuprh wake-up pending register high 00 116 r255 wuprl wake-up pending register low 00 116 60 std int r245 simrh interrupt mask register high (ch. i to l) 00 105 r246 simrl interrupt mask register low (ch. e to h) 00 105 r247 sitrh interrupt trigger register high (ch. i to l) 00 105 r248 sitrl interrupt trigger register low (ch. e to h) 00 105 r249 siprh interrupt pending register high (ch. i to l) 00 105 r250 siprl interrupt pending register low (ch. e to h) 00 105 r251 sivr interrupt vector register (ch. e to l) xe 106 r252 siplrh interrupt priority register high (ch. i to l) ff 106 r253 siplrl interrupt priority register low (ch. e to h) ff 106 r254 sflagrh interrupt flag register high (ch. i to l) 00 107 r255 siflagrl interrupt flag register low (ch. e to h) 00 107 page (dec) block reg. no. register name description reset value hex. doc. page 9
86/398 st92f124/f150/f250 - register and memory map 61 adc r240 d0hr channel 0 data high register xx 362 r241 d0lr channel 0 data low register x0 362 r242 d1hr channel 1 data high register xx 362 r243 d1lr channel 1 data low register x0 362 r244 d2hr channel 2 data high register xx 362 r245 d2lr channel 2 data low register x0 362 r246 d3hr channel 3 data high register xx 362 r247 d3lr channel 3 data low register x0 362 r248 d4hr channel 4 data high register xx 363 r249 d4lr channel 4 data low register x0 363 r250 d5hr channel 5 data high register xx 363 r251 d5lr channel 5 data low register x0 363 r252 d6hr channel 6 data high register xx 363 r253 d6lr channel 6 data low register x0 363 r254 d7hr channel 7 data high register xx 363 r255 d7lr channel 7 data low register x0 363 62 r240 d8hr channel 8 data high register xx 364 r241 d8lr channel 8 data low register x0 364 r242 d9hr channel 9 data high register xx 364 r243 d9lr channel 9 data low register x0 364 r244 d10hr channel 10 data high register xx 364 r245 d10lr channel 10 data low register x0 364 r246 d11hr channel 11 data high register xx 364 r247 d11lr channel 11 data low register x0 364 r248 d12hr channel 12 data high register xx 365 r249 d12lr channel 12 data low register x0 365 r250 d13hr channel 13 data high register xx 365 r251 d13lr channel 13 data low register x0 365 r252 d14hr channel 14 data high register xx 365 r253 d14lr channel 14 data low register x0 365 r254 d15hr channel 15 data high register xx 365 r255 d15lr channel 15 data low register x0 365 page (dec) block reg. no. register name description reset value hex. doc. page 9
87/398 st92f124/f150/f250 - register and memory map note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. * available on some devices only 63 adc r243 crr compare result register 0x 366 r244 ltahr channel a lower threshold high register xx 366 r245 ltalr channel a lower threshold low register x0 366 r246 ltbhr channel b lower threshold high register xx 366 r247 ltblr channel b lower threshold low register x0 367 r248 utahr channel a upper threshold high register xx 367 r249 utalr channel a upper threshold low register x0 367 r250 utbhr channel b upper threshold high register xx 367 r251 utblr channel b upper threshold low register x0 367 r252 clr1 control logic register 1 0f 368 r253 clr2 control logic register 2 a0 368 r254 ad_icr interrupt control register 0f 369 r255 ad_ivr interrupt vector register x2 370 page (dec) block reg. no. register name description reset value hex. doc. page 9
88/398 st92f124/f150/f250 - interrupts 5 interrupts 5.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine. the st9 cpu can receive requests from the fol- lowing sources: C on-chip peripherals C external pins C top-level pseudo-non-maskable interrupt 5.1.1 on-chip peripheral interrupt sources 5.1.1.1 dedicated channels the following on-chip peripherals have dedicated interrupt channels with interrupt control registers located in their peripheral register page. C a/d converter C i 2 c C jpbld C mft C sci-m 5.1.1.2 standard channels other on-chip peripherals have their interrupts mapped to the intxx interrupt channel group. these channels have control registers located in pages 0 and 60. these peripherals are: C can C e 3 tm /flash C eft timer C rccu C sci-a C spi C stim timer C wdt timer C wuimu 5.1.1.3 external interrupts up to eight external interrupts, with programmable input trigger edge, are available and are mapped to the intxx interrupt channel group in page 0. 5.1.1.4 top level interrupt (tli) in addition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the external nmi pin (where available) to provide a non-maskable interrupt, or to the timer/watch- dog. interrupt service routines are addressed through a vector table mapped in memory. figure 40. interrupt response n 5.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages (or in register page 0 or 60 if it is mapped to one of the intxx channels). the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit 9
89/398 st92f124/f150/f250 - interrupts the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). if an external watchdog is used, refer to the regis- ter and memory map section for details on using vector locations 0006h to 0009h. otherwise loc- tions 0006h to 0007h must contain ffffh. with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 5.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). 5.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select between original st9 backward compati- bility mode and st9+ interrupt management mode. st9 backward compatibility mode (encsr = 0) if encsr is reset, the cpu works in original st9 compatibility mode. for the duration of the inter- rupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. st9+ mode (encsr = 1) if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. encsr bit 0 1 mode st9 compatible st9+ pushed/popped registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments 9
90/398 st92f124/f150/f250 - interrupts 5.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: C the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). C the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 5.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests (interrupts or dma). if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 5.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 5.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. 5.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel with the highest position in the chain, as shown in table 18 table 18. daisy chain priority * available on some devices only 5.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to dynamically modify the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 41 . highest position lowest position inta0 / watchdog timer inta1 / standard timer intb0 / extended function timer 0 * intb1 / extended function timer 1 * intc0 / e 3 tm /flash intc1 / spi intd0 / rccu intd1 / wkup mgt multifunction timer 0 inte0/can0_rx0 inte1/can0_rx1 intf0/can0_tx intf1/can0_sce intg0/can1_rx0 * intg1/can1_rx1 * inth0/can1_tx * inth1/can1_sce * inti0/sci-a * jblpd * i 2 c bus interface 0 i 2 c bus interface 1 * a/d converter multifunction timer 1 sci-m 9
91/398 st92f124/f150/f250 - interrupts figure 41. example of dynamic priority level modification in nested mode 5.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 5.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routines priority. this may cause undesirable interrupt response sequences. 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program 9
92/398 st92f124/f150/f250 - interrupts arbitration modes (contd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 42 ) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 42. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request 9
93/398 st92f124/f150/f250 - interrupts arbitration modes (contd) example 2 in the second example, (more complex, figure 43 ), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 43. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei 9
94/398 st92f124/f150/f250 - interrupts arbitration modes (contd) 5.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C cpl is saved in the special nicr stack to hold the priority level of the suspended routine. C priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 44. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request 9
95/398 st92f124/f150/f250 - interrupts arbitration modes (contd) end of interrupt routine the iret interrupt return instruction executes the following steps: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. C if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 44 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 45 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level. figure 45. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei 9
96/398 st92f124/f150/f250 - interrupts 5.6 external interrupts the st9 core contains 8 external interrupt sources grouped into four pairs. table 19. external interrupt channel grouping each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to 1, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 47 . figure 46. priority level examples the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2,prl1. for each pair, the even chan- nel (a0,b0,c0,d0) of the group has the even prior- ity level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 46 shows an example of priority levels. figure 47 and table 20 give an overview of the ex- ternal interrupts and vectors. table 20. multiplexed interrupt sources C the source of inta0 can be selected between the external pin int0 or the timer/watchdog pe- ripheral using the ia0s bit in the eivr register (r246 page 0). C the source of inta1 can be selected between the external pin int1 or the standard timer us- ing the ints bit in the stc register (r232 page 11). C the source of intb0 can be selected between the external pin int2 or the on-chip extended function timer 0 using the eftis bit in the cr3 register (r255 page 28). C the source of intb1 can be selected between external pin int3 or the on-chip extended func- tion timer 1 using the eftis bit in the cr3 reg- ister (r255 page 29). C the source of intc0 can be selected between external pin int4 or the on-chip e 3 tm /flash memory using bit feien in the ecr register (ad- dress 224001h). C the source of intc1 can be selected between external pin int5 or the on-chip spi using the spis bit in the spcr0 register (r241 page 7). C the source of intd0 can be selected between external pin int6 or the reset and clock unit rccu using the int_sel bit in the clkctl reg- ister (r240 page 55). C the source of intd1 can be selected between the nmi pin and the wuimu wakeup/interrupt lines using the id1s bit in the wucrtl register (r248 page 9). warning : when using external interrupt channels shared by both external interrupts and peripherals, special care must be taken to configure control registers both for peripheral and interrupts. external interrupt channel i/o port pin wkup[0:15] intd1 p8[1:0] p7[7:5] p6[7,5] p5[7:5, 2:0] p4[7,4] int6 int5 int4 int3 int2 int1 int0 intd0 intc1 intc0 intb1 intb0 inta1 inta0 p6.1 p6.3 p6.2 p6.3 p6.2 p6.0 p6.0 1 00 1 00 1 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priority source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr 0 100=4 101=5 channel internal interrupt source external interrupt inta0 timer/watchdog int0 inta1 standard timer int1 intb0 extended function timer 0 int2 intb1 extended function timer 1 int3 intc0 e 3 tm /flash int4 intc1 spi interrupt int5 intd0 rccu int6 intd1 wake-up management unit 9
97/398 st92f124/f150/f250 - interrupts external interrupts (contd) figure 47. external interrupt control bits and vectors * only four interrupt pins are available. refer to table 19 for i/o pin mapping. int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 0 0 x x x 0 0 1 ia0s watchdog/timer end of count int 0 pin* int a1 request int 6 pin int b0 request int 2 pin* int b1 request teb1 int 3 pin* int c0 request int c1 request int d0 request int d1 request vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 x x x 1 v7 v6 v5 v4 0 1 0 x x x 0 v7 v6 v5 v4 0 1 1 x x x 1 v7 v6 v5 v4 1 0 0 x x x 0 v7 v6 v5 v4 1 0 1 x x x 1 v7 v6 v5 v4 1 1 0 x x x 0 v7 v6 v5 v4 1 1 1x x x 1 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 spis spi 1 0 ints stim timer 1 0 int_sel rccu 0 1 tea0 teb0 0 1 ted0 eftis eft1 timer 0 1 1 0 eftis eft0 timer 1 0 id1s nmi wake-up controller wkup (0:15) e 3 tm /flash feien int 4 pin* int 5 pin* int 1 pin* tea1 tec0 tec1 9
98/398 st92f124/f150/f250 - interrupts 5.7 standard interrupts (can and sci-a) the two on-chip can peripherals generate 4 inter- rupt sources each. the sci-a interrupts are mapped on a single interrupt channel. the map- ping is shown in the following table. table 21. interrupt channel assignment 5.7.1 functional description the siprl and siprh registers contain the inter- rupt pending bits of the interrupt sources. the pending bits are set by hardware on occurrence of a rising edge event. the pending bits are reset by hardware when the interrupt is acknowledged. the simrl and simrh registers are used to mask the interrupt requests coming from the inter- rupt sources. resetting the bits of these registers prevents the interrupt requests being sent to the st9 core. the sitrl and sitrh registers are used to select the edge sensitivity of the interrupt channel (rising or falling edge). as the sci-a and can interrupt events are rising edge events, all bits in the sitrl register and itei0 bit in sitrh register must be set to 1. the priority level of the interrupt channels can be programmed to one of eight priority levels using the siplrl and siplrh control registers. the two msbs of the priority level are user pro- grammable. for each interrupt group, the even channels (e0, f0, g0, h0, i0) have an even priority level (lsb of priority level is zero) and the odd channels (e1, f1, g1, h1) have an odd priority lev- el (the lsb of priority level is one). see figure 48 . . figure 48. priority level examples all interrupt channels share a single interrupt vec- tor register (sivr). bits 1 to 4 of the sivr register change according to the interrupt channel which has the highest priority pending interrupt request. if more than one interrupt channel has pending in- terrupt requests with the same priority, then an in- ternal daisy chain decides the interrupt channel that will be served. inte0 is first in the internal dai- sy chain and inti0 is last. an overrun flag is associated with each interrupt channel. if a new interrupt request comes before the earlier interrupt request is acknowledged then the corresponding overrun flag is set. interrupt pairs interrupt source inte0 inte1 can0_rx0 can0_rx1 intf0 intf1 can0_tx can0_sce intg0 intg1 can1_rx0 can1_rx1 inth0 inth1 can1_tx can1_sce inti0 inti1 sci-a reserved 1 00 1 00 1 pl2h pl1h pl2g pl1g pl2f pl1f pl2e pl1e int.g1: int.h1: 001=1 int.g0: source priority priority source int.e0: 010=2 int.e1: 011=3 int.f1: 101=5 int.f0: 100=4 int.h0: 000=0 iplrl 0 100=4 101=5 9
99/398 st92f124/f150/f250 - interrupts figure 49. standard interrupt (channels e to i) control bits and vectors int e0 request vector priority level mask bit pending bit ime0 ipe0 v7 v6 v5 0 0 0 0 x x x 0 int e1 request int f0 request int f1 request int g0 request int g1 request int h0 request int h1 request vector priority level mask bit pending bit ime1 ipe1 v7 v6 v5 0 0 0 1 x x x 1 v7 v6 v5 0 0 1 0 x x x 0 v7 v6 v5 0 0 1 1 x x x 1 v7 v6 v5 0 1 0 0 x x x 0 v7 v6 v5 0 1 0 1 x x x 1 v7 v6 v5 0 1 1 0 x x x 0 v7 v6 v5 0 1 1 1 x x x 1 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imf0 pending bit ipf0 pending bit ipf1 pending bit ipg0 pending bit ipg1 pending bit iph0 pending bit iph1 mask bit imf1 mask bit img0 mask bit img1 mask bit imh0 mask bit imh1 itee0 itef0 iteh0 itrx0 itee1 iteg0 iteg1 itef1 can_0 * iteh1 itrx1 ittx itsce itrx0 can_1 * itrx1 ittx itsce int i0 request v7 v6 v5 1 0 0 0 x x x 0 vector priority level pending bit ipi0 mask bit imi0 itei0 sci-a * * on some devices only 9
100/398 st92f124/f150/f250 - interrupts 5.8 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt or dma request, in any arbitration mode, not even by a subsequent top level interrupt request. warning . the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. fur- thermore the tli never modifies the cpl bits and the nicr register. 5.9 dedicated on-chip peripheral interrupts some of the on-chip peripherals have their own specific interrupt unit containing one or more inter- rupt channels, or dma channels. please refer to the specific peripheral chapter for the description of its interrupt features and control registers. the on-chip peripheral interrupts are controlled by the following bits: C interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. C interrupt mask bit (im). if im = 0, no interrupt request is generated. if im =1 an interrupt re- quest is generated whenever ip = 1 and cicr.ien = 1. C priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) C interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. 9
101/398 st92f124/f150/f250 - interrupts figure 50. top level interrupt structure n n 5.10 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay. watchdog enable wdgen watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request 9
102/398 st92f124/f150/f250 - interrupts 5.11 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable. this bit enables the 16-bit multifunction timer pe- ripheral. 0: mft disabled 1: mft enabled bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generared when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bits 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event 70 gcen tlip tli ien iam cpl2 cpl1 cpl0 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0 9
103/398 st92f124/f150/f250 - interrupts interrupt registers (contd) external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bits 7:6 = pl2d, pl1d: intd0, d1 priority level. bis 5:4 = pl2c, pl1c : intc0, c1 priority level. bits 3:2 = pl2b, pl1b : intb0, b1 priority level. bits 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest) 9
104/398 st92f124/f150/f250 - interrupts interrupt registers (contd) external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bits 7:4 = v[7:4] : most significant nibble of exter- nal interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 47 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source (the ia0s bit must be set in this case) 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source (the tlis bit must be set in this case) 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bits 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0 9
105/398 st92f124/f150/f250 - interrupts interrupt registers (contd) interrupt mask register high (simrh) r245 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:1 = reserved. bit 0 = imi0 channel i mask bit the imi0 bit is set and cleared by software to ena- ble or disable interrupts on channel i0 . 0: interrupt masked 1: an interrupt is generated if the ipi0 bit is set in the siprh register. interrupt mask register low (simrl) r246 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:0 = imxx channel e to h mask bits the imxx bits are set and cleared by software to enable or disable on channel xx interrupts. 0: interrupt masked 1: an interrupt is generated if the corresponding ipxx bit is set in the siprl register. interrupt trigger event register high (sitrh) r247 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:1 = reserved. bit 0 = itei0 channel i0 trigger event this bit is set and cleared by software to define the polarity of the channel i0 trigger event 0: the i0 pending bit will be set on the falling edge of the interrupt line 1: the i0 pending bit will be set on the rising edge of the interrupt line note: the itei0 bit must be set to enable the sci- a interrupt as the sci-a interrupt event is a rising edge event. interrupt trigger event register low (sitrl) r248 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:0 = itexx channel e to h trigger event the itexx bits are set and cleared by software to define the polarity of the channel xx trigger event 0: the corresponding pending bit will be set on the falling edge of the interrupt line 1: the corresponding pending bit will be set on the rising edge of the interrupt line note: the itexx bits must be set to enable the can interrupts as the can interrupt events are ris- ing edge events. note: if either a rising or a falling edge occurs on the interrupt lines during a write access to the iter register, the pending bit will not be set. interrupt pending register high (siprh) r249 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:1 = reserved. bit 0 = ipi0 channel i0 pending bit the ipi0 bit is set by hardware on occurrence of the trigger event. (as specified in the itr register) and is cleared by hardware on interrupt acknowl- edge. 0 : no interrupt pending 1 : interrupt pending 70 ---- - - -imi0 70 imh1 imh0 img1 img0 imf1 imf0 ime1 ime0 70 ---- - - -itei0 70 iteh1 iteh0 iteg1 iteg0 itef1 itef0 itee1 itee0 70 ---- - - -ipi0 9
106/398 st92f124/f150/f250 - interrupts interrupt registers (contd) interrupt pending register low (siprl) r250 - read/write register page: 60 reset value: 0000 0000 (00h) bits 7:0 = ipxx channel e-h pending bits the ipxx bits are set by hardware on occurrence of the trigger event. (as specified in the itr regis- ter) and are cleared by hardware on interrupt ac- knowledge. 0 : no interrupt pending 1 : interrupt pending note: ipr bits may be set by the user to imple- ment a software interrupt. standard interrupt vector register (sivr) r251 - read/write register page: 60 reset value: xxx1 1110 (xe ) bits 7:5 = v[7:5] msbs of channnel e to l inter- rupt vector address these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:5], refer to figure 49 . bits 4:1 = w[3:0] arbitration winner bits these bits are set and cleared by hardware de- pending upon the channel which emerges as a winner as shown in the following table. at the start of interrupt/dma arbitration (ic0 = 0) the w[3:0] bits are latched. they remain stable through the entire arbitration cycle. even if a inter- rupt of higher priority comes after the start of int/ dma arbitration, the sivr register is not updated. this new request will be taken into account in the next arbitration cycle. bit 0 = reserved, fixed by hardware to 0. interrupt priority level register high (siplrh) r252 - read/write register page: page 60 reset value : 1111 1111 bits 1:0 = pl2i, pl1i : inti0, i1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for even channels and at 1 for odd channels 70 iph1 iph0 ipg1 ipg0 ipf1 ipf0 ipe1 ipe0 70 v7 v6 v5 w3 w2 w1 w0 0 interrupt channel pair w[3:0] inte0 inte1 0000 0001 intf0 intf1 0010 0011 intg0 intg1 0100 0101 inth0 inth1 0110 0111 inti0 1000 70 - - - - - - pl2i pl1i 9
107/398 st92f124/f150/f250 - interrupts interrupt registers (contd) interrupt priority level register low (siplrl) r253 - read/write register page: page 60 reset value : 1111 1111 bits 7:6 = pl2h, pl1h: inth0,h1 priority level. bits 5:4 = pl2g, pl1g : intg0, g1 priority level. bits 3:2 = pl2f, pl1f : intf0, f1 priority level. bits 1:0 = pl2e, pl1e : inte0, e1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for even channels and at 1 for odd channels table 22. pl bit assignment table 23. pl bit meaning interrupt flag register high (sflagrh) r254 - read only register page: 60 reset value : 0000 0000 bit 0 = oufi0 : overrun flag for inti0 this bit is set and cleared by hardware. it indicates if more than one interrupt event occured on inti0 before the ipi0 bit in the siprh register has been cleared. 0 : no overrun 1 : overrun has occurred on inti0 interrupt flag register low (sflagrl) r255 - read only register page: 60 reset value : 0000 0000 bits 7:0 = oufxx : overrun flag for channel xx these bits are set and cleared by hardware. they indicate if more than one interrupt event occurs on the associated channel before the pending bit in the siprl register has been cleared. 0 : no overrun 1 : overrun has occurred on channel xx 70 pl2h pl1h pl2g pl1g pl2f pl1f pl2e pl1e interrupt channel pair 3-bit priority level inth0 inth1 pl2h pl2h pl1h pl1h 0 1 intg0 intg1 pl2g pl2g pl1g pl1g 0 1 intf0 intf1 pl2f pl2f pl1f pl1f 0 1 inte0 inte1 pl2e pl2e pl1e pl1e 0 1 pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest) interrupt channel pair priority level inte0 inte1 pl2e pl2e pl1e pl1e 0 1 intf0 intf1 pl2f pl2f pl1f pl1f 0 1 intg0 intg1 pl2g pl2g pl1g pl1g 0 1 inth0 inth1 pl2h pl2h pl1h pl1h 0 1 70 -- - ----oufi0 70 oufh1 oufh0 oufg1 oufg0 ouff1 ouff0 oufe1 oufe0 9
108/398 st92f124/f150/f250 - interrupts interrupt registers (contd) table 25. standard interrupt channel register map (page 60) address register name 76543210 r245 simrh reset value 0000000 imi0 0 r246 simrl reset value imh1 0 imh0 0 img1 0 img0 0 imf1 0 imf0 0 ime1 0 ime0 0 r247 sitrh reset value 00000 0 0 itei0 0 r248 sitrl reset value iteh1 0 iteh0 0 iteg1 0 iteg0 0 itef1 0 itef0 0 itee1 0 itee0 0 r249 siprh reset value 00 00000 ipi0 0 r250 siprl reset value iph1 0 iph0 0 ipg1 0 ipg0 0 ipf1 0 ipf0 0 ipe1 0 ipe0 0 r251 sivr reset value v2 x v1 x v0 x w3 1 w2 1 w1 1 w0 1 0 0 r252 siplrh reset value 000000 pl2i 1 pl1i 1 r253 siplrl reset value pl2h 1 pl1h 1 pl2g 1 pl1g 1 pl2f 1 pl1f 1 pl2e 1 pl1e 1 r254 sflagrh reset value 00 00 0 00 ouf0 0 r255 sflagrl reset value ouf7 0 ouf6 0 ouf5 0 ouf4 0 ouf3 0 ouf2 0 ouf1 0 ouf0 0 9
109/398 st92f124/f150/f250 - interrupts 5.12 wake-up / interrupt lines management unit (wuimu) 5.12.1 introduction the wake-up/interrupt management unit extends the number of external interrupt lines from 8 to 23 (depending on the number of external interrupt lines mapped on external pins of the device). it al- lows the source of the intd1 external interrupt channel to be selected between the int7 pin (when available) and up to 16 additional external wake-up/interrupt pins. these 16 wkup pins can be programmed as ex- ternal interrupt lines or as wake-up lines, able to exit the microcontroller from low power mode (stop mode) (see figure 51 ). 5.12.2 main features n supports up to 16 additional external wake-up or interrupt lines n wake-up lines can be used to wake-up the st9 from stop mode. n programmable selection of wake-up or interrupt n programmable wake-up trigger edge polarity n all wake-up lines maskable note: the number of available pins is device de- pendent. refer to the device pinout description. figure 51. wake-up lines / interrupt management unit block diagram wutrh wutrl wuprh wuprl wumrh wumrl triggering level registers pending request registers mask registers wkup[7:0] wkup[15:8] 10 set nmi wuctrl sw setting 1) wkup-int id1s stop to cpu reset to rccu - stop mode control to cpu intd1 - external interrupt channel int7 note 1: the reset signal on the stop bit is stronger than the set signal. 9
110/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) 5.12.3 functional description 5.12.3.1 interrupt mode to configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. configure the mask bits of the 16 wake-up lines (wumrl, wumrh) 2. configure the triggering edge registers of the wake-up lines (wutrl, wutrh) 3. set bit 7 of eimr (r244 page 0) and eitr (r242 page 0) registers of the cpu: so an interrupt coming from one of the 16 lines can be correctly acknowledged 4. reset the wkup-int bit in the wuctrl regis- ter to disable wake-up mode 5. set the id1s bit in the wuctrl register to dis- able the int7 external interrupt source and enable the 16 wake-up lines as external inter- rupt source lines. to return to standard mode (int7 external inter- rupt source enabled and 16 wake-up lines disa- bled) it is sufficient to reset the id1s bit. 5.12.3.2 wake-up mode selection to configure the 16 lines as wake-up sources, use the following procedure: 1. configure the mask bits of the 16 wake-up lines (wumrl, wumrh). 2. configure the triggering edge registers of the wake-up lines (wutrl, wutrh). 3. set, as for interrupt mode selection, bit 7 of eimr and eitr registers only if an interrupt routine is to be executed after a wake-up event. otherwise, if the wake-up event only restarts the execution of the code from where it was stopped, the intd1 interrupt channel must be masked or the external source must be selected by resetting the id1s bit. 4. since the rccu can generate an interrupt request when exiting from stop mode, take care to mask it even if the wake-up event is only to restart code execution. 5. set the wkup-int bit in the wuctrl register to select wake-up mode 6. set the id1s bit in the wuctrl register to dis- able the int7 external interrupt source and enable the 16 wake-up lines as external inter- rupt source lines. this is not mandatory if the wake-up event does not require an interrupt response. 7. write the sequence 1,0,1 to the stop bit of the wuctrl register with three consecutive write operations. this is the stop bit setting sequence. to detect if stop mode was entered or not, im- mediately after the stop bit setting sequence, poll the rccu ex_stp bit (r242.7, page 55) and the stop bit itself. 5.12.3.3 stop mode entry conditions assuming the st9 is in run mode: during the stop bit setting sequence the following cases may occur: case 1: nmi = 0, wrong stop bit setting se- quence this can happen if an interrupt/dma request is ac- knowledged during the stop bit setting se- quence. in this case polling the stop and ex_stp bits will give: stop = 0, ex_stp = 0 this means that the st9 did not enter stop mode due to a bad stop bit setting sequence: the user must retry the sequence. case 2: nmi = 0, correct stop bit setting se- quence in this case the st9 enters stop mode. there are two ways to exit stop mode: 1. a wake-up interrupt (not an nmi interrupt) is acknowledged. that implies: stop = 0, ex_stp = 1 this means that the st9 entered and exited stop mode due to an external wake-up line event. 2. a nmi rising edge woke up the st9. this implies: stop = 1, ex_stp = 1 this means that the st9 entered and exited stop mode due to an nmi (rising edge) event. the user should clear the stop bit via software. 9
111/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) case 3: nmi = 1 (nmi kept high during the 3rd write instruction of the sequence), bad stop bit setting sequence the result is the same as case 1: stop = 0, ex_stp = 0 this means that the st9 did not enter stop mode due to a bad stop bit setting sequence: the user must retry the sequence. case 4: nmi = 1 (nmi kept high during the 3rd write instruction of the sequence), correct stop bit setting sequence in this case: stop = 1, ex_stp = 0 this means that the st9 did not enter stop mode due to nmi being kept high. the user should clear the stop bit via software. note: if nmi goes to 0 before resetting the stop bit, the st9 will not enter stop mode. case 5: a rising edge on the nmi pin occurs during the stop bit setting sequence. the nmi interrupt will be acknowledged and the st9 will not enter stop mode. this implies: stop = 0, ex_stp = 0 this means that the st9 did not enter stop mode due to an nmi interrupt serviced during the stop bit setting sequence. at the end of nmi routine, the user must re-enter the sequence: if nmi is still high at the end of the sequence, the st9 can not enter stop mode (see nmi pin management on page 112.). case 6: a wake-up event on the external wake- up lines occurs during the stop bit setting se- quence there are two possible cases: 1. interrupt requests to the cpu are disabled: in this case the st9 will not enter stop mode, no interrupt service routine will be executed and the program execution continues from the instruction following the stop bit setting sequence. the status of stop and ex_stp bits will be again: stop = 0, ex_stp = 0 the application can determine why the st9 did not enter stop mode by polling the pending bits of the external lines (at least one must be at 1). 2. interrupt requests to cpu are enabled: in this case the st9 will not enter stop mode and the interrupt service routine will be executed. the status of stop and ex_stp bits will be again: stop = 0, ex_stp = 0 the interrupt service routine can determine why the st9 did not enter stop mode by polling the pending bits of the external lines (at least one must be at 1). if the mcu really exits from stop mode, the rccu ex_stp bit is still set and must be reset by software. otherwise, if nmi was high or an inter- rupt/dma request was acknowledged during the stop bit setting sequence, the rccu ex_stp bit is reset. this means that the mcu has filtered the stop mode entry request. the wkup-int bit can be used by an interrupt routine to detect and to distinguish events coming from interrupt mode or from wake-up mode, allow- ing the code to execute different procedures. to exit stop mode, it is sufficient that one of the 16 wake-up lines (not masked) generates an event: the clock restarts after the delay needed for the oscillator to restart. the same effect is obtained when a rising edge is detected on the nmi pin, which works as a 17th wake-up line. note: after exiting from stop mode, the software can successfully reset the pending bits (edge sen- sitive), even though the corresponding wake-up line is still active (high or low, depending on the trigger event register programming); the user must poll the external pin status to detect and dis- tinguish a short event from a long one (for example keyboard input with keystrokes of varying length). 9
112/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) 5.12.3.4 nmi pin management on the cpu side, if tltev=1 (top level trigger event, bit 3 of register r246, page 0) then a rising edge on the nmi pin will set the tlip bit (top level interrupt pending bit, r230.6). at this point an in- terrupt request to the cpu is given either if tl- nm=1 (top level not maskable bit, r247.7 - once set it can only be cleared by reset) or if tli=1 and ien=1 (bits r230.5, r230.4). assuming that the application uses a non-maska- ble top level interrupt (tlnm=1): in this case, whenever a rising edge occurs on the nmi pin, the related service routine will be executed. to service further top level interrupt requests, it is neces- sary to generate a new rising edge on the external nmi pin. the following summarizes some typical cases: C if the st9 is in stop mode and a rising edge on the nmi pin occurs, the st9 will exit stop mode and the nmi service routine will be exe- cuted. C if the st9 is in run mode and a rising edge oc- curs on the nmi pin: the nmi service routine is executed and then the st9 restarts the execu- tion of the main program. now, suppose that the user wants to enter stop mode with nmi still at 1. the st9 will not enter stop mode and it will not execute an nmi routine be- cause there were no transitions on the exter- nal nmi line . C if the st9 is in run mode and a rising edge on nmi pin occurs during the stop bit setting se- quence: the nmi interrupt will be acknowledged and the st9 will not enter stop mode. at the end of the nmi routine, the user must re-enter the sequence: if nmi is still high at the end of the sequence, the st9 can not enter stop mode (see previous case). C if the st9 is in run mode and the nmi pin is high: if nmi is forced low just before the third write in- struction of the stop bit setting sequence then the st9 will enter stop mode. 9
113/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) 5.12.4 programming considerations the following paragraphs give some guidelines for designing an application program. 5.12.4.1 procedure for entering/exiting stop mode 1. program the polarity of the trigger event of external wake-up lines by writing registers wutrh and wutrl. 2. check that at least one mask bit (registers wumrh, wumrl) is equal to 1 (so at least one external wake-up line is not masked). 3. reset at least the unmasked pending bits: this allows a rising edge to be generated on the intd1 channel when the trigger event occurs (an interrupt on channel intd1 is recognized when a rising edge occurs). 4. select the interrupt source of the intd1 chan- nel (see description of id1s bit in the wuctrl register) and set the wkup-int bit. 5. to generate an interrupt on channel intd1, bits eitr.1 (r242.7, page 0) and eimr.1 (r244.7, page 0) must be set and bit eipr.7 must be reset. bits 7 and 6 of register r245, page 0 must be written with the desired priority level for interrupt channel intd1. 6. reset the stop bit in register wuctrl and the ex_stp bit in the clk_flag register (r242.7, page 55). refer to the rccu chapter. 7. to enter stop mode, write the sequence 1, 0, 1 to the stop bit in the wuctrl register with three consecutive write operations. 8. the code to be executed just after the stop sequence must check the status of the stop and rccu ex_stp bits to determine if the st9 entered stop mode or not (see wake-up mode selection on page 110. for details). if the st9 did not enter in stop mode it is necessary to reloop the procedure from the beginning, oth- erwise the procedure continues from next point. 9. poll the wake-up pending bits to determine which wake-up line caused the exit from stop mode. 10.clear the wake-up pending bit that was set. 5.12.4.2 simultaneous setting of pending bits it is possible that several simultaneous events set different pending bits. in order to accept subse- quent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this operation allows a rising edge to be generated on the intd1 line (if there is at least one more pend- ing bit set and not masked) and so to set eipr.7 bit again. a further interrupt on channel intd1 will be serviced depending on the status of bit eimr.7. two possible situations may arise: 1. the user chooses to reset all pending bits: no further interrupt requests will be generated on channel intd1. in this case the user has to: C reset eimr.7 bit (to avoid generating a spuri- ous interrupt request during the next reset op- eration on the wuprh register) C reset wuprh register using a read-modify- write instruction (and, bres, band) C clear the eipr.7 bit C reset the wuprl register using a read-mod- ify-write instruction (and, bres, band) 2. the user chooses to keep at least one pending bit active: at least one additional interrupt request will be generated on the intd1 chan- nel. in this case the user has to reset the desired pending bits with a read-modify-write instruction (and, bres, band). this operation will generate a rising edge on the intd1 chan- nel and the eipr.7 bit will be set again. an interrupt on the intd1 channel will be serviced depending on the status of eimr.7 bit. 9
114/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) 5.12.5 register description wake-up control register ( wuctrl) r249 - read/write register page: 57 reset value: 0000 0000 (00h) bit 2 = stop: stop bit. to enter stop mode, write the sequence 1,0,1 to this bit with three consecutive write operations . when a correct sequence is recognized, the stop bit is set and the rccu puts the mcu in stop mode. the software sequence succeeds only if the following conditions are true: C the nmi pin is kept low, C the wkup-int bit is 1, C all unmasked pending bits are reset C at least one mask bit is equal to 1 (at least one external wake-up line is not masked). otherwise the mcu cannot enter stop mode, the program code continues executing and the stop bit remains cleared. the bit is reset by hardware if, while the mcu is in stop mode, a wake-up interrupt comes from any of the unmasked wake-up lines. the bit is kept high if, during stop mode, a rising edge on nmi pin wakes up the st9. in this case the user should reset it by software. the stop bit is at 1 in the four following cases (see wake-up mode selection on page 110. for details): C after the first write instruction of the sequence (a 1 is written to the stop bit) C at the end of a successful sequence (i.e. after the third write instruction of the sequence) C the st9 entered and exited stop mode due to a rising edge on the nmi pin. in this case the ex_stp bit in the clk_flag is at 1 (see rccu chapter). C the st9 did not enter stop mode due to the nmi pin being kept high. in this case rccu bit ex_stp is at 0 note : the stop request generated by the wuimu (that allows the st9 to enter stop mode) is ored with the external stop pin (active low). this means that if the external stop pin is forced low, the st9 will enter stop mode independently of the status of the stop bit. warnings : C writing the sequence 1,0,1 to the stop bit will enter stop mode only if no other register write instructions are executed during the sequence. if interrupt or dma requests (which always perform register write operations) are acknowledged dur- ing the sequence, the st9 will not enter stop mode: the user must re-enter the sequence to set the stop bit. C whenever a stop request is issued to the mcu, a few clock cycles are needed to enter stop mode (see rccu chapter for further details). hence the execution of the instruction following the stop bit setting sequence might start before entering stop mode: if such instruction per- forms a register write operation, the st9 will not enter in stop mode. in order to avoid to execute register write instructions after a correct stop bit setting sequence and before entering the stop mode, it is mandatory to execute 3 nop instructions after the stop bit setting sequence. bit 1 = id1s: interrupt channel intd1 source. this bit is set and cleared by software. 0: int7 external interrupt source selected, exclud- ing wake-up line interrupt requests 1: the 16 external wake-up lines enabled as inter- rupt sources, replacing the int7 external pin function warning: to avoid spurious interrupt requests on the intd1 channel due to changing the inter- rupt source, use this procedure to modify the id1s bit: 1. mask the intd1 interrupt channel (bit 7 of reg- ister eimr - r244, page 0 - reset to 0). 2. program the id1s bit as needed. 3. clear the ipd1 interrupt pending bit (bit 7 of register eipr - r243, page 0) 4. remove the mask on intd1 (bit eimr.7=1). bit 0 = wkup-int: wakeup interrupt. this bit is set and cleared by software. 0: the 16 external wakeup lines can be used to generate interrupt requests 1: the 16 external wake-up lines to work as wake- up sources for exiting from stop mode 70 -----stopid1swkup-int 9
115/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) wake-up mask register high ( wumrh) r250 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wum[15:8]: wake-up mask bits. if wumx is set, an interrupt on channel intd1 and/or a wake-up event (depending on id1s and wkup-int bits) are generated if the correspond- ing wupx pending bit is set. more precisely, if wumx=1 and wupx=1 then: C if id1s=1 and wkup-int=1 then an interrupt on channel intd1 and a wake-up event are gener- ated. C if id1s=1 and wkup-int=0 only an interrupt on channel intd1 is generated. C if id1s=0 and wkup-int=1 only a wake-up event is generated. C if id1s=0 and wkup-int=0 neither interrupts on channel intd1 nor wake-up events are gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7. if wumx is reset, no wake-up events can be gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7 (resetting id1s bit to 0). wake-up mask register low ( wumrl) r251 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wum[7:0]: wake-up mask bits. if wumx is set, an interrupt on channel intd1 and/or a wake-up event (depending on id1s and wkup-int bits) are generated if the correspond- ing wupx pending bit is set. more precisely, if wumx=1 and wupx=1 then: C if id1s=1 and wkup-int=1 then an interrupt on channel intd1 and a wake-up event are gener- ated. C if id1s=1 and wkup-int=0 only an interrupt on channel intd1 is generated. C if id1s=0 and wkup-int=1 only a wake-up event is generated. C if id1s=0 and wkup-int=0 neither interrupts on channel intd1 nor wake-up events are gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7. if wumx is reset, no wake-up events can be gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7 (resetting id1s bit to 0). 70 wum15 wum14 wum13 wum12 wum11 wum10 wum9 wum8 70 wum7 wum6 wum5 wum4 wum3 wum2 wum1 wum0 9
116/398 st92f124/f150/f250 - interrupts wake-up / interrupt lines management unit (contd) wake-up trigger register high ( wutrh) r252 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wut[15:8]: wake-up trigger polarity bits these bits are set and cleared by software. 0: the corresponding wupx pending bit will be set on the falling edge of the input wake-up line . 1: the corresponding wupx pending bit will be set on the rising edge of the input wake-up line. wake-up trigger register low ( wutrl) r253 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wut[7:0]: wake-up trigger polarity bits these bits are set and cleared by software. 0: the corresponding wupx pending bit will be set on the falling edge of the input wake-up line. 1: the corresponding wupx pending bit will be set on the rising edge of the input wake-up line. warning 1. as the external wake-up lines are edge trig- gered, no glitches must be generated on these lines. 2. if either a rising or a falling edge on the external wake-up lines occurs while writing the wutrlh or wutrl registers, the pending bit will not be set. wake-up pending register high ( wuprh) r254 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wup[15:8]: wake-up pending bits these bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. they must be cleared by software. they can be set by software to implement a software inter- rupt. 0: no wake-up trigger event occurred 1: wake-up trigger event occured wake-up pending register low ( wuprl) r255 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wup[7:0]: wake-up pending bits these bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. they must be cleared by software. they can be set by software to implement a software inter- rupt. 0: no wake-up trigger event occurred 1: wake-up trigger event occured note: to avoid losing a trigger event while clear- ing the pending bits, it is recommended to use read-modify-write instructions (and, bres, band) to clear them. 70 wut15 wut14 wut13 wut12 wut11 wut10 wut9 wut8 70 wut7 wut6 wut5 wut4 wut3 wut2 wut1 wut0 70 wup15 wup14 wup13 wup12 wup11 wup10 wup9 wup8 70 wup7 wup6 wup5 wup4 wup3 wup2 wup1 wup0 9
117/398 st92f124/f150/f250 - on-chip direct memory access (dma) 6 on-chip direct memory access (dma) 6.1 introduction the st9 includes on-chip direct memory access (dma) in order to provide high-speed data transfer between peripherals and memory or register file. multi-channel dma is fully supported by peripher- als having their own controller and dma chan- nel(s). each dma channel transfers data to or from contiguous locations in the register file, or in memory. the maximum number of bytes that can be transferred per transaction by each dma chan- nel is 222 with the register file, or 65536 with memory. the dma controller in the peripheral uses an indi- rect addressing mechanism to dma pointers and counter registers stored in the register file. this is the reason why the maximum number of trans- actions for the register file is 222, since two reg- isters are allocated for the pointer and counter. register pairs are used for memory pointers and counters in order to offer the full 65536 byte and count capability. 6.2 dma priority levels the 8 priority levels used for interrupts are also used to prioritize the dma requests, which are ar- bitrated in the same arbitration phase as interrupt requests. if the event occurrence requires a dma transaction, this will take place at the end of the current instruction execution. when an interrupt and a dma request occur simultaneously, on the same priority level, the dma request is serviced before the interrupt. an interrupt priority request must be strictly higher than the cpl value in order to be acknowledged, whereas, for a dma transaction request, it must be equal to or higher than the cpl value in order to be executed. thus only dma transaction requests can be acknowledged when the cpl=0. dma requests do not modify the cpl value, since the dma transaction is not interruptable. figure 52. dma data transfer peripheral vr001834 data address counter transferred register file or memory register file register file start address counter value 0 df data group f peripheral paged registers 9
118/398 st92f124/f150/f250 - on-chip direct memory access (dma) 6.3 dma transactions the purpose of an on-chip dma channel is to transfer a block of data between a peripheral and the register file, or memory. each dma transfer consists of three operations: C a load from/to the peripheral data register to/ from a location of register file (or memory) ad- dressed through the dma address register (or register pair) C a post-increment of the dma address register (or register pair) C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. if the dma transaction is carried out between the peripheral and the register file ( figure 53 ), one register is required to hold the dma address, and one to hold the dma transaction counter. these two registers must be located in the register file: the dma address register in the even address register, and the dma transaction counter in the next register (odd address). they are pointed to by the dma transaction counter pointer register (dcpr), located in the peripherals paged regis- ters. in order to select a dma transaction with the register file, the control bit dcpr.rm (bit 0 of dcpr) must be set. if the transaction is made between the peripheral and memory , a register pair (16 bits) is required for the dma address and the dma transaction counter ( figure 54 ). thus, two register pairs must be located in the register file. the dma transaction counter is pointed to by the dma transaction counter pointer register (dcpr), the dma address is pointed to by the dma address pointer register (dapr),both dcpr and dapr are located in the paged regis- ters of the peripheral. figure 53. dma between register file and peripheral idcr ivr dapr dcpr data paged registers registers system dma counter dma address ffh f0h e0h dfh efh memory 000000h data already transferred end of block interrupt service routine dma table dma transaction isr address 000100h vector table register file peripheral paged registers 9
119/398 st92f124/f150/f250 - on-chip direct memory access (dma) dma transactions (contd) when selecting the dma transaction with memory, bit dcpr.rm (bit 0 of dcpr) must be cleared. to select between using the isr or the dmasr reg- ister to extend the address, (see memory manage- ment unit chapter), the control bit dapr.ps (bit 0 of dapr) must be cleared or set respectively. the dma transaction counter must be initialized with the number of transactions to perform and will be decremented after each transaction. the dma address must be initialized with the starting ad- dress of the dma table and is increased after each transaction. these two registers must be located between addresses 00h and dfh of the register file. once a dma channel is initialized, a transfer can start. the direction of the transfer is automatically defined by the type of peripheral and programming mode. once the dma table is completed (the transaction counter reaches 0 value), an interrupt request to the cpu is generated. when the interrupt pending (idcr.ip) bit is set by a hardware event (or by software), and the dma mask bit (idcr.dm) is set, a dma request is gen- erated. if the priority level of the dma source is higher than, or equal to, the current priority level (cpl), the dma transfer is executed at the end of the current instruction. dma transfers read/write data from/to the location pointed to by the dma address register, the dma address register is in- cremented and the transaction counter register is decremented. when the contents of the trans- action counter are decremented to zero, the dma mask bit (dm) is cleared and an interrupt request is generated, according to the interrupt mask bit (end of block interrupt). this end-of-block inter- rupt request is taken into account, depending on the prl value. warning . dma requests are not acknowledged if the top level interrupt service is in progress. figure 54. dma between memory and peripheral n idcr ivr dapr dcpr data paged registers registers system dma transaction counter dma address ffh f0h e0h dfh efh memory 000000h data already transferred end of block interrupt service routine dma table dma transaction isr address 000100h vector table register file peripheral paged registers 9
120/398 st92f124/f150/f250 - on-chip direct memory access (dma) dma transactions (contd) 6.4 dma cycle time the interrupt and dma arbitration protocol func- tions completely asynchronously from instruction flow. requests are sampled every 5 cpuclk cycles. dma transactions are executed if their priority al- lows it. a dma transfer with the register file requires 8 cpuclk cycles. a dma transfer with memory requires 16 cpuclk cycles, plus any required wait states. 6.5 swap mode an extra feature which may be found on the dma channels of some peripherals (e.g. the multifunc- tion timer) is the swap mode. this feature allows transfer from two dma tables alternatively. all the dma descriptors in the register file are thus dou- bled. two dma transaction counters and two dma address pointers allow the definition of two fully in- dependent tables (they only have to belong to the same space, register file or memory). the dma transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the dma controller automatically swaps to the other table (table 1) by pointing to the other dma descriptors. in this case, the dma mask (dm bit) control bit is not cleared, but the end of block interrupt request is generated to allow the optional updating of the first data table (table 0). until the swap mode is disabled, the dma control- ler will continue to swap between dma table 0 and dma table 1. n 9
121/398 st92f124/f150/f250 - on-chip direct memory access (dma) 6.6 dma registers as each peripheral dma channel has its own spe- cific control registers, the following register list should be considered as a general example. the names and register bit allocations shown here may be different from those found in the peripheral chapters. dma counter pointer register (dcpr) read/write address set by peripheral reset value: undefined bit 7:1 = c[7:1] : dma transaction counter point- er. software should write the pointer to the dma transaction counter in these bits. bit 0 = rm : register file/memory selector. this bit is set and cleared by software. 0: dma transactions are with memory (see also dapr.dp) 1: dma transactions are with the register file generic external peripheral inter- rupt and dma control (idcr) read/write address set by peripheral reset value: undefined bit 5 = ip : interrupt pending . this bit is set by hardware when the trigger event occurs. it is cleared by hardware when the request is acknowledged. it can be set/cleared by software in order to generate/cancel a pending request. 0: no interrupt pending 1: interrupt pending bit 4 = dm : dma request mask . this bit is set and cleared by software. it is also cleared when the transaction counter reaches zero (unless swap mode is active). 0: no dma request is generated when ip is set. 1: dma request is generated when ip is set bit 3 = im : end of block interrupt mask . this bit is set and cleared by software. 0: no end of block interrupt request is generated when ip is set 1: end of block interrupt is generated when ip is set. dma requests depend on the dm bit value as shown in the table below. bit 2:0 = prl[2:0] : source priority level . these bits are set and cleared by software. refer to section 6.2 dma priority levels for a de- scription of priority levels. dma address pointer register (dapr) read/write address set by peripheral reset value: undefined bit 7:1 = a[7:1] : dma address register(s) pointer software should write the pointer to the dma ad- dress register(s) in these bits. bit 0 = ps : memory segment pointer selector : this bit is set and cleared by software. it is only meaningful if dcpr.rm=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). 70 c7 c6 c5 c4 c3 c2 c1 rm 70 ip dm im prl2 prl1 prl0 dm im meaning 10 a dma request generated without end of block interrupt when ip=1 11 a dma request generated with end of block in- terrupt when ip=1 00 no end of block interrupt or dma request is generated when ip=1 01 an end of block interrupt is generated without associated dma request (not used) prl2 prl1 prl0 source priority level 0000 h ighest 0011 0102 0113 1004 1015 1106 1117 lo west 70 a7 a6 a5 a4 a3 a2 a1 ps 9
122/398 st92f124/f150/f250 - reset and clock control unit (rccu) 7 reset and clock control unit (rccu) 7.1 introduction the reset and clock control unit (rccu) com- prises two distinct sections: C the clock control unit, which generates and manages the internal clock signals. C the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. on st9 devices where the external stop pin and/ or the wake-up interrupt manager unit are availa- ble, this circuit also detects and manages the stop mode during which all oscillators are frozen in or- der to achieve the lowest possible power con- sumption (refer to the reset/stop mode and wake-up interrupt manager unit description). 7.2 clock control unit the clock control unit generates the internal clocks for the cpu core (cpuclk) and for the on- chip peripherals (intclk). the clock control unit may be driven by the on-chip oscillator (provided an external crystal circuit is connected to the os- cin and oscout pins), or by an external pulse generator, connected to oscout (see figure 62 and figure 64 ). when significant power reduction is required, a low frequency external clock may be selected. to do this, this clock source must be connected to the ck_af pin. 7.2.1 clock control unit overview as shown in figure 55 a programmable divider can divide the clock1 input clock signal by two. in practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the pll multiplier circuit. the resulting signal, clock2, is the reference input clock to the pro- grammable phase locked loop frequency multi- plier, which is capable of multiplying the clock fre- quency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a programmable divider, by a factor of 1 to 7. by these means, the st9 can operate with cheaper, medium frequency (3-5 mhz) crystals, while still providing a high frequen- cy internal clock for maximum system perform- ance; the range of available multiplication and divi- sion factors allow a great number of operating clock frequencies to be derived from a single crys- tal frequency. for low power operation, especially in wait for in- terrupt mode, the clock multiplier unit may be turned off, whereupon the output clock signal may be programmed as clock2 divided by 16. for further power reduction, a low frequency external clock connected to the ck_af pin may be select- ed, whereupon the crystal controlled main oscilla- tor may be turned off. the internal system clock, intclk, is routed to all on-chip peripherals, as well as to the programma- ble clock prescaler unit which generates the clock for the cpu core (cpuclk). (see figure 55 ) the clock prescaler is programmable and can slow the cpu clock by a factor of up to 8, allowing the programmer to reduce cpu processing speed, and thus power consumption, while maintaining a high speed clock to the peripherals. this is partic- ularly useful when little actual processing is being done by the cpu and the peripherals are doing most of the work. figure 55. clock control unit simplified block diagram crystal ck_af 1/16 1/2 oscillator source clock2 clock1 ck_af pll clock multiplier cpu clock prescaler to cpu core to peripherals cpuclk intclk unit /divider 9
123/398 st92f124/f150/f250 - reset and clock control unit (rccu) figure 56. st92f124/f150/f250 clock distribution diagram clock1 pll 1/16 x 1/2 div2 1/ n mx(1:0) csu_cksel 6/8/10/14 xt_div16 dx(2:0) 1/4 ck_128 0 1 0 1 rccu intclk clock2 stim 1/4 8-bit prescaler 16-bit down counter 1...256 3-bit prescaler cpu mftx 1/3 8-bit prescaler 16-bit up/down counter 1...256 txina/txinb (max intclk/3) eftx 1/n 16-bit up counter extclkx (max intclk/4) n=2,4,8 baud rate generator 1/n n = 2...(2 16 -1) sci-m 3-bit prescaler 1...8 baud rate generator 1/n n=2,4,16,32 sck master sck slave (max intclk/2) spi logic jblpd cpuclk embedded memory ram eprom flash e 3 tm i 2 c std fast 1/n 1/n n=4,6,8...258 n=6,9,12...387 fscl 100 khz fscl 400 khz fscl > 100 khz 1...8 sci-a 6-bit prescaler 1...64 p6.5 1/2 1/16 p6.0 1/8 p4.1 16-bit down counter 1/4 wdg 8-bit prescaler 1...256 j1850 kernel ckaf_sel 01 01 ck_af 2-bit prescaler adc 3-bit prescaler 1...8 3-bit prescaler 3-bit prescaler 8-bit prescaler 8-bit prescaler 1,3,4,13 1...128 1...256 can baud rate 1...64 prescaler wdin clock2/8 p7.0 9
124/398 st92f124/f150/f250 - reset and clock control unit (rccu) 7.3 clock management the various programmable features and operating modes of the ccu are handled by four registers: C moder (mode register) this is a system register (r235, group e). the input clock divide-by-two and the cpu clock prescaler factors are handled by this register. C clkctl (clock control register) this is a paged register (r240, page 55). the low power modes, the rccu interrupts and the interpretation of the halt instruction are handled by this register. C clk_flag (clock flag register) this is a paged register (r242, page 55). this register contains various status flags, as well as control bits for clock selection. C pllconf (pll configuration register) this is a paged register (r246, page 55). pll management is programmed in this register. figure 57. clock control unit programming crystal pll ck_af 1/16 x 1/2 div2 ckaf_sel 1/n oscillator mx[1:0] 0 1 0 1 0 1 source ckaf_st csu_cksel 6/8/10/14 1 0 xt_div16 dx[2:0] clock2 clock1 (moder) (clk_flag) (clkctl) (pllconf) (clk_flag) ck_af intclk to peripherals and cpu clock prescaler xtstop (clk_flag) wait for interrupt and low power modes: lpowfi (clkctl) selects low power operation automatically on entering wfi mode. wfi_cksel (clkctl) selects the ck_af clock automatically, if present, on entering wfi mode. xtstop (clk_flag) automatically stops the crystal oscillator when the ck_af clock is present and selected. 1/4 ck_128 9
125/398 st92f124/f150/f250 - reset and clock control unit (rccu) clock management (contd) 7.3.1 pll clock multiplier programming the clock1 signal generated by the oscillator drives a programmable divide-by-two circuit. if the div2 control bit in moder is set (reset condi- tion), clock2, is equal to clock1 divided by two; if div2 is reset, clock2 is identical to clock1. since the input clock to the clock multi- plier circuit requires a 50% duty cycle for correct pll operation, the divide by two circuit should be enabled when a crystal oscillator is used, or when the external clock generator does not provide a 50% duty cycle. in practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the pll multiplier circuit. when the pll is active, it multiplies clock2 by 6, 8, 10 or 14, depending on the status of the mx[0:1] bits in pllconf. the multiplied clock is then di- vided by a factor in the range 1 to 7, determined by the status of the dx[0:2] bits; when these bits are programmed to 111, the pll is switched off. following a reset phase, programming bits dx0-2 to a value different from 111 will turn the pll on. after allowing a stabilization period for the pll, setting the csu_cksel bit in the clk_flag register selects the multiplier clock. the rccu contains a frequency comparator be- tween clock2 and the pll clock output that ver- ifies if the pll reaches the programmed frequency and has stabilized (locked status). when this con- dition occurs, the lock bit in the clk_flag reg- ister is set to 1 by hardware and this value is main- tained as long as the pll is locked. the lock bit is set back to 0 if for some reason (change of mx bit value, stop and restart of pll or clock2, etc.), the pll loses the programmed frequency in which it was locked. the pll selection as system clock is further con- ditioned by the status of the voltage regulator: when it is not providing a stabilized supply voltage, the pll cannot be selected. the maximum frequency allowed for intclk is 24 mhz. care is required, when programming the pll multiplier and divider factors, not to exceed the maximum permissible operating frequency for intclk, according to supply voltage , as reported in electrical characteristics section. the st9 being a static machine, there is no lower limit for intclk. however, some peripherals have their own minimum internal clock frequency limit below which the functionality is not guaranteed. 7.3.2 pll free running mode the pll is able to provide a 50-khz clock, usable to slow program execution. this mode is controlled by the freen and dx[2:0] bits in the pllconf register: when the pll is off and the freen bit is set to 1 (i.e. when the freen and dx[2:0] bits are set to 1), the pll provides this clock. the selection of this clock is also managed by the csu_cksel bit but is not conditioned by the lock bit. to avoid unpredictable behaviour of the pll clock, free running mode must be set and reset by the user only when the pll clock is not the system clock, i.e. when the csu_cksel bit is reset. in addition, when the pll provides the internal clock, if the clock signal disappears (for instance due to a broken or disconnected resonator...), a safety clock signal is automatically provided, al- lowing the st9 to perform some rescue opera- tions. typ. safety clock frequency = 800 khz / div, where div depends on the dx[0..2] bits of the pll- conf register (r246, page55). table 26. free running clock frequency dx2 dx1 dx0 div ck (typ.) 0 0 0 2 400 khz 0 0 1 4 200 khz 0 1 0 6 133 khz 0 1 1 8 100 khz 1 0 0 10 80 khz 1 0 1 12 67 khz 1 1 0 14 57 khz 11116 50 khz (csu_cksel=0; freen=1) 111 - clock2 (csu_cksel=0; freen=0) 9
126/398 st92f124/f150/f250 - reset and clock control unit (rccu) clock management (contd) 7.3.3 cpu clock prescaling the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, drives a programmable prescaler which generates the basic time base, cpuclk, for the instruction executer of the st9 cpu core. this allows the user to slow down program execu- tion during non processor intensive routines, thus reducing power dissipation. the internal peripherals are not affected by the cpuclk prescaler and continue to operate at the full intclk frequency. this is particularly useful when little processing is being done and the pe- ripherals are doing most of the work. the prescaler divides the input clock by the value programmed in the control bits prs2,1,0 in the moder register. if the prescaler value is zero, no prescaling takes place, thus cpuclk has the same period and phase as intclk. if the value is different from 0, the prescaling is equal to the val- ue plus one, ranging thus from two (prs[2:0] = 1) to eight (prs[2:0] = 7). the clock generated is shown in figure 58 , and it will be noted that the prescaling of the clock does not preserve the 50% duty cycle, since the high level is stretched to replace the missing cycles. this is analogous to the introduction of wait cycles for access to external memory. when external memory wait or bus request events occur, cpu- clk is stretched at the high level for the whole pe- riod required by the function figure 58. cpu clock prescaling n 7.3.4 peripheral clock the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, is also routed to all st9 on-chip pe- ripherals and acts as the central timebase for all timing functions. 7.3.5 low power modes the user can select an automatic slowdown of clock frequency during wait for interrupt opera- tion, thus idling in low power mode while waiting for an interrupt. in wfi operation the clock to the cpu core is stopped, thus suspending program execution, while the clock to the peripherals may be programmed as described in the following par- agraphs. two examples of low power operation in wfi are illustrated in figure 59 and figure 60 . providing that low power operation during wait for interrupt is enabled (by setting the lpowfi bit in the clkctl register), as soon as the cpu exe- cutes the wfi instruction, the pll is turned off and the system clock will be forced to clock2 divided by 16, or to the external low frequency clock, ck_af, if this has been selected by setting wfi_cksel, and providing ckaf_st is set, thus indicating that the external clock is selected and actually present on the ck_af pin. if the external clock source is used, the crystal os- cillator may be stopped by setting the xtstop bit, providing that the ck_af clock is present and se- lected, indicated by ckaf_st being set. in this case, the crystal oscillator will be stopped auto- matically on entering wfi if the wfi_cksel bit has been set. it should be noted that selecting a non-existent ck_af clock source is impossible, since such a selection requires that the auxiliary clock source be actually present and selected. in no event can a non-existent clock source be selected inadvert- ently. it is up to the user program to switch back to a fast- er clock on the occurrence of an interrupt, taking care to respect the oscillator and pll stabilization delays, as appropriate. it should be noted that any of the low power modes may also be selected explicitly by the user pro- gram even when not in wait for interrupt mode, by setting the appropriate bits. if the freen bit is set, the pll is not stopped dur- ing low power wfi, increasing power consump- tion. intclk cpuclk va00260 000 001 010 011 100 101 110 111 prs value 9
127/398 st92f124/f150/f250 - reset and clock control unit (rccu) clock management (contd) 7.3.6 interrupt generation system clock selection modifies the clkctl and clk_flag registers. the clock control unit generates an external inter- rupt request (intd0) in the following conditions: C when ck_af and clock2/16 are selected or deselected as system clock source, C when the system clock restarts after a hardware stop (when the stop mode feature is availa- ble on the specific device). C when the pll loses the programmed frequency in which it was locked, and when it re-locks this interrupt can be masked by resetting the int_sel bit in the clkctl register. note that this is the only case in the st9 where an interrupt is generated with a high to low transition. table 27. summary of operating modes using main crystal controlled oscillator mode intclk cpuclk div2 prs0-2 csu_cksel mx0-1 dx2-0 lpowfi wfi_ck sel xt_div16 pll x by 14 xtal/2 x (14/d) intclk/ n 1 n-1 1 1 0 d-1 x x 1 pll x by 10 xtal/2 x (10/d) intclk/ n 1 n-1 1 0 0 d-1 x x 1 pll x by 8 xtal/2 x (8/d) intclk/ n 1 n-1 1 1 1 d-1 x x 1 pll x by 6 xtal/2 x (6/d) intclk/ n 1 n-1 1 0 1 d-1 x x 1 slow 1 xtal/2 intclk/ n 1n-1xx111xx1 slow 2 xtal/32 intclk/ n 1n-1xxxxx0 slow3 ck_af ck_af/n x n-1 x x x x x x wfi if lpowfi=0, no changes occur on intclk, but cpuclk is stopped anyway. low pow- er wfi 1 xtal/32 stop 1 x x x x 1 0 x low pow- er wfi 2 ck_af stop 1 x x x x 1 1 x reset xtal/2 intclk 1 0 0 00 111 0 0 1 example xtal=4.4 mhz 2.2*10/2 = 11mhz 11mhz 1 0 1 00 001 x 1 9
128/398 st92f124/f150/f250 - reset and clock control unit (rccu) figure 59. example of low power mode programming in wfi using ck_af external clock users program wfi instruction program flow intclk frequency interrupt pll multiply factor divider factor set wait for the pll to lock ck_af clock selected wait for interrupt no code is executed until interrupt serviced set to 10 to 1, and pll turned on an interrupt is requested low power mode enabled 2 mhz 20 mhz 2 mhz 20 mhz ** t 2 = quartz oscillator start-up time * t 1 = pll lock-in time t 1 * t 2 ** f xtal = 4 mhz wait csu_cksel ? 1 pll is system clock source while ck_af is the system clock and the xtal restarts f ck_af the system clock switches to xtal in wfi state in wfi state users program preselect xtal stopped when ck_af selected activated wait for the xtal wait pll is system clock source to stabilise wait for the pll to lock wait wfi_cksel ? 1 xtstop ? 1 lpowfi ? 1 wfi status interrupt routine xtstop ? 0 ckaf_sel ? 0 csu_cksel ? 1 dx[2:0] ? 000 mx[1:0] ? 00 reset state ck_af selected and xtal stopped automatically begin execution of user program resumes at full speed 9
129/398 st92f124/f150/f250 - reset and clock control unit (rccu) figure 60. example of low power mode programming in wfi using clock2/16 users program wfi instruction program flow intclk frequency interrupt pll multiply factor divider factor set wait for the pll to lock wait for interrupt no code is executed until interrupt serviced set to 6 to 1, and pll turned on an interrupt is requested low power mode enabled 2 mhz 12 mhz 2 mhz 12 mhz * t 1 = pll lock-in time t 1 * t 1 * f xtal = 4 mhz wait csu_cksel ? 1 pll is system clock source pll switched on 125 khz in wfi state users program activated pll is system clock source wait for the pll to lock wait lpowfi ? 1 wfi status interrupt routine csu_cksel ? 1 dx[2:0] ? 000 mx[1:0] ? 01 reset state clock2/16 selected and pll automatically begin clock2 selected stopped execution of user program resumes at full speed 9
130/398 st92f124/f150/f250 - reset and clock control unit (rccu) 7.4 clock control registers mode register (moder) r235 - read/write system register reset value: 1110 0000 (e0h) *note : this register contains bits which relate to other functions; these are described in the chapter dealing with device architecture. only those bits relating to clock functions are described here. bit 5 = div2 : crystal oscillator clock divided by 2 . this bit controls the divide by 2 circuit which oper- ates on clock1. 0: no division of clock1 1: clock1 is internally divided by 2 bits 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to pres- cale cpuclk from intclk. when these three bits are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. clock control register (clkctl) r240 - read write register page: 55 reset value: 0000 0000 (00h) bit 7 = int_sel : interrupt selection . 0: the external interrupt channel input signal is se- lected (reset state) 1: select the internal rccu interrupt as the source of the interrupt request bits 6:4 = reserved for test purposes must be kept reset for normal operation. bit 3 = sresen : software reset enable. 0: the halt instruction turns off the quartz, the pll and the ccu 1: a reset is generated when halt is executed bit 2 = ckaf_sel : alternate function clock se- lect. 0: ck_af clock not selected 1: select ck_af clock note: to check if the selection has actually oc- curred, check that ckaf_st is set. if no clock is present on the ck_af pin, the selection will not occur. bit 1 = wfi_cksel : wfi clock select . this bit selects the clock used in low power wfi mode if lpowfi = 1. 0: intclk during wfi is clock2/16 1: intclk during wfi is ck_af, providing it is present. in effect this bit sets ckaf_sel in wfi mode warning : when the ck_af is selected as low power wfi clock but the crystal is not turned off (r242.4 = 0), after exiting from the wfi, ck_af will be still selected as system clock. in this case, reset the r240.2 bit to switch back to the crystal oscillator clock. bit 0 = lpowfi : low power mode during wait for interrupt . 0: low power mode during wfi disabled. when wfi is executed, the cpuclk is stopped and intclk is unchanged 1: the st9 enters low power mode when the wfi instruction is executed. the clock during this state depends on wfi_cksel 70 - - div2 prs2 prs1 prs0 - - 70 int_s el --- sre- sen ckaf_s el wfi_cks el lpow fi 9
131/398 st92f124/f150/f250 - reset and clock control unit (rccu) clock control registers (contd) clock flag register (clk_flag) r242 -read/write register page: 55 reset value: 0110 1000 after a flash lvd reset reset value: 0100 1000 after a watchdog reset reset value: 0010 1000 after a software reset reset value: 0000 1000 after an external reset warning : if you select the ck_af as system clock and turn off the oscillator (bits r240.2 and r242.4 at 1), in order to switch back to the crystal clock by resetting the r240.2 bit, you must first wait for the oscillator to restart correctly. bit 7 = ex_stp : external stop flag. this bit is set by hardware/software and cleared by software. 0: no external stop condition occurred 1: external stop condition occurred note : this bit is set after the end of the instruction being executed when the microcontroller enters stop mode. so, if this instruction is a reading of the clk_flag register, this bit will still be read as 0. next reading will give 1 as result. bit 6 = wdgres : watchdog reset flag. this bit is read only. 0: no watchdog reset occurred 1: watchdog reset occurred bit 5 = softres : software reset flag. this bit is read only. 0: no software reset occurred 1: software reset occurred (halt instruction) if both softres and wdgres are set to 1, the last reset event generator was a flash lvd reset. table 28. reset flags bit 4 = xtstop : external stop enable. 0: external stop disabled 1: the xtal oscillator will be stopped as soon as the ck_af clock is present and selected, whether this is done explicitly by the user pro- gram, or as a result of wfi, if wfi_cksel has previously been set to select the ck_af clock during wfi. note: when the program writes 1 to the xtstop bit, it will still be read as 0 as long as the ckaf_st bit is reset (ckaf_st=0). in this case, take care of this behaviour, because a subsequent and with 1 or a or with 0 to the xstop bit before setting the ckaf_st bit will prevent the oscillator from being stopped. bit 3 = xt_div16 : clock/16 selection. this bit is set and cleared by software. an interrupt is generated when the bit is toggled. 0: clock2/16 is selected and the pll is off 1: the input is clock2 (or the pll output de- pending on the value of csu_cksel) bit 2 = ckaf_st : (read only) if set, indicates that the alternate function clock has been selected. if no clock signal is present on the ck_af pin, the selection will not occur. if re- set, the pll clock, clock2 or clock2/16 is se- lected (depending on bit 0). bit 1= lock : pll locked-in this bit is read only. 0: the pll is turned off or not locked and cannot be selected as system clock source. 1: the pll is locked bit 0 = csu_cksel : csu clock select. this bit is set and cleared by software. it is also cleared by hardware when: C bits dx[2:0] (pllconf) are set to 111; C the quartz is stopped (by hardware or software); C wfi is executed while the lpowfi bit is set; C the xt_div16 bit (clk_flag) is forced to 0. this prevents the pll, when not yet locked, from providing an irregular clock. furthermore, a 0 stored in this bit speeds up the plls locking. 0: clock2 provides the system clock 1: the pll multiplier provides the system clock if the lock bit is set to 1 if the freen bit is set, this bit selects this clock in- dependently by the lock bit. note : setting the ckaf_sel bit overrides any other clock selection. resetting the xt_div16 bit overrides the csu_cksel selection (see figure 57). 70 ex_ stp wdg res soft res xt- stop xt_ div16 ckaf_ st lo ck csu_ ck- sel wdgres softres 0 0 1 1 0 1 0 1 external reset software reset watchdog reset lvd reset 9
132/398 st92f124/f150/f250 - reset and clock control unit (rccu) clock control registers (contd) pll configuration register (pllconf) r246 - read/write register page: 55 reset value: 0x00 x111 bit 7 = freen : pll free running mode enable 0: pll free running mode disabled 1: pll free running mode enabled when this bit is set, even if the dx[2:0] bits are all set to 1, the pll is not stopped but provides a slow frequency back-up clock, selectable by the csu_cksel bit of the clk_flag register (with- out needing to have the lock bit equal to 1). bits 5:4 = mx[1:0] : pll multiplication factor . refer to table 29 for multiplier settings. warning: after these bits are modified, take care that the pll lock-in time has elapsed before setting the csu_cksel bit in the clk_flag reg- ister. bits 2:0 = dx[2:0] : pll output clock divider factor. refer to table 30 for divider settings. 70 freen 0 mx1 mx0 0 dx2 dx1 dx0 table 29. pll multiplication factors mx1 mx0 clock2 x 10 14 00 10 11 8 01 6 table 30. pll divider factors dx2 dx1 dx0 ck 0 0 0 pll clock/1 0 0 1 pll clock/2 0 1 0 pll clock/3 0 1 1 pll clock/4 1 0 0 pll clock/5 1 0 1 pll clock/6 1 1 0 pll clock/7 111 clock2 (pll off, reset state) 9
133/398 st92f124/f150/f250 - reset and clock control unit (rccu) figure 61. rccu general timing pll multiplier clock2 intclk internal reset clock pll switched on by user 20479 x clock1 pll lock-in time exit from reset pll selected by user boot rom execution user program execution reset phase filtered external reset < 4s 20s vr02113b external reset 9
134/398 st92f124/f150/f250 - reset and clock control unit (rccu) 7.5 crystal oscillator the on-chip components for the crystal oscillator are an inverting circuit, polarised at the trip point. the inverter is built around an n-channel transis- tor, loaded with a current source and polarised through a feedback resistor. the current source is tailored to obtain a pseudo sinusoidal signal at oscout and oscin, reduc- ing the electromagnetic emission. the inverter stage is followed by a matching inverter, which is followed in turn by a schmitt-triggered buffer. in halt mode, set by means of the halt instruc- tion, in stop mode, and under control of the xt- stop bit, the oscillator is disabled. the current sources are switched off, reducing the power dis- sipation. the internal clock, clock1, is forced to a high level. to exit the halt condition and restart the oscilla- tor, an external reset pulse is required, having a a minimum duration of t stup (see figure 66 and section 11 electrical characteristics ). it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied. figure 62. crystal oscillator table 31. maximum r s values legend : c 1 , c 2 : maximum total capacitances on pins oscin and oscout (the value includes the external capacitance tied to the pin plus the parasitic capacitance of the board and of the device) note : the tables are relative to the fundamental quartz crystal only (not ceramic resonator). figure 63. internal oscillator schematic figure 64. external clock oscin oscout c 1 c 2 st9 crystal clock *rd can be inserted to reduce the drive level, rd * when using low drive crystals . hildi tl c 1 =c 2 freq. 33pf 22pf 5 mhz 80 130 4 mhz 120 200 3 mhz 220 370 oscout r pol v dd i load oscin clock1 oscout oscin clock input external clock vr02116b st9 9
135/398 st92f124/f150/f250 - reset and clock control unit (rccu) ceramic resonators murata electronics ceralock resonators have been tested with the st92f150 at 3, 3.68, 4 and 5 mhz. these recommended resonators have built-in capacitors (see table 32 ). the test circuit is shown in figure 65 . figure 65. test circuit table 32 shows the recommended conditions at different frequencies. table 32. obtained results advantages of using ceramic resonators : cstcr and cstcc types have built-in loading capacitors. smallest loading capacitor resonators are recom- mended for standard applications. highest loading capacitor resonators are recom- mended for automotive applications with can and tight frequency tolerance. test conditions : the evaluation conditions are 4.5 to 5.5 v for the supply voltage and -40 to 105 c for the tempera- ture range. caution: these circuit conditions are for design reference only. recommended c1, c2 value depends on the cir- cuit board used. for tight frequency tolerance applications, please contact the nearest murata office for more de- tailled pcb evaluation regarding layout. note 1: attention must be paid to leakage currents around the oscin pin. leakage paths from v dd could al- ter the dc polarization of the inverter stage and in- troduce a mismatch with the second stage, and possibly stop the clock signal. it is recommended to surround the oscillator components by a ground ring on the printed circuit board and if necessary to apply a coating film to avoid humidity problems. note 2: attention must be paid to the capacitive loading of oscout. oscout must not be used to drive ex- ternal circuits. v dd c1 c2 oscin ceralock st92f150 rd oscout v ss freq. (mhz) parts number c1 (pf) c2 (pf) rd (ohm) 5 cstcr5m00g55a-r0 39 39 0 cstcc5m00g56a-r0 47 47 0 4 cstcr4m00g55a-r0 39 39 0 cstcc4m00g56a-r0 47 47 0 3 cstcc3m00g56a-r0 47 47 0 3.68 cstcc3m68g56a-r0 47 47 0 9
136/398 st92f124/f150/f250 - reset and clock control unit (rccu) 7.6 reset/stop manager the reset/stop manager resets the mcu when one of the three following events occurs: C a hardware reset, initiated by a low level on the reset pin. C a software reset, initiated by a halt instruction (when enabled with the sr esen bit of the clkctl register). C a watchdog end of count condition. the event which caused the last reset is flagged in the clk_flag register, by setting either the softres or the wdgres bit or both; a hard- ware initiated reset will leave both these bits reset. the hardware reset overrides all other conditions and forces the st9 to the reset state. during re- set, the internal registers are set to their reset val- ues (when these reset values are defined, other- wise the register content will remain unchanged), and the i/o pins are set to bidirectional weak-pull- up or high impedance input. see section 7.3 . reset is asynchronous: as soon as the reset pin is driven low, a reset cycle is initiated. figure 66. oscillator start-up sequence and reset timing v dd max v dd min oscin intclk reset oscout pin t stup vr02085a 9
137/398 st92f124/f150/f250 - reset and clock control unit (rccu) reset/stop manager (contd) the on-chip timer/watchdog generates a reset condition if the watchdog mode is enabled (wcr.wdgen cleared, r252 page 0), and if the programmed period elapses without the specific code (aah, 55h) written to the appropriate register. the input pin reset is not driven low by the on- chip reset generated by the timer/watchdog. when the reset pin goes high again, 20479 oscil- lator clock cycles (clock1) are counted before ex- iting the reset state ( + one possible clock1 pe- riod, depending on the delay between the rising edge of the reset pin and the first rising edge of clock1). subsequently a short boot routine is ex- ecuted from the device internal boot memory, and control then passes to the user program. the boot routine sets the device characteristics and loads the correct values in the memory man- agement units pointer registers, so that these point to the physical memory areas as mapped in the specific device. the precise duration of this short boot routine varies from device to device, depending on the boot memory contents. at the end of the boot routine the program coun- ter will be set to the location specified in the reset vector located in the lowest two bytes of memory. 7.6.1 reset pin timing to improve the noise immunity of the device, the reset pin has a schmitt trigger input circuit with hysteresis. in addition, a filter will prevent an un- wanted reset in case of a single glitch of less than 50 ns on the reset pin. the device is certain to re- set if a negative pulse of more than 20 m s is ap- plied. when the reset pin goes high again, a delay of up to 4 m s will elapse before the rccu detects this rising front. from this event on, a defined number of clock1 cycles (refer to t rsph ) is counted before exiting the reset state ( + one pos- sible clock1 period depending on the delay be- tween the positive edge the rccu detects and the first rising edge of clock1). if the st9 is a romless version, without on-chip program memory, the memory interface ports are set to external memory mode (i.e alternate func- tion) and the memory accesses are made to exter- nal program memory with wait cycles insertion. if the voltage regulator is present in the device, please ensure the reset pin is released only when the internal voltage supply is stabilized at 3.3v. figure 67. recommended signal to be applied on reset pin figure 68. reset pin input structure v resetn v dd v ihrs v ilrs 20 m s minimum pin e sd protection circuitry schmitt trigger and low pass filter to generate reset signal 9
138/398 st92f124/f150/f250 - external memory interface (extmi) 8 external memory interface (extmi) 8.1 introduction the st9 external memory interface uses two reg- isters (emr1 and emr2) to configure external memory accesses. some interface signals are also affected by wcr - r252 page 0. if the two registers emr1 and emr2 are set to the proper values, the st9+ memory access cycle is similar to that of the original st9, with the only ex- ception that it is composed of just two system clock phases, named t1 and t2. during phase t1, the memory address is output on the as falling edge and is valid on the rising edge of as . port1 and port 9 maintain the address sta- ble until the following t1 phase. during phase t2, two forms of behavior are possi- ble. if the memory access is a read cycle, port 0 pins are released in high-impedance until the next t1 phase and the data signals are sampled by the st9 on the rising edge of ds . if the memory ac- cess is a write cycle, on the falling edge of ds , port 0 outputs data to be written in the external memory. those data signals are valid on the rising edge of ds and are maintained stable until the next address is output. note that ds is pulled low at the beginning of phase t2 only during an external memory access. figure 69. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu ext.mem page 21 mmu bit dprrem=0 sspl ssph uspl usph moder ppr rp1 rp0 flagr cicr p5 p4 p3 p2 p1 p0 dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 bit dprrem=1 sspl ssph uspl usph moder ppr rp1 rp0 flagr cicr p5 p4 p3 p2 p1 p0 dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p0-3 and dpr0-3 registers 9
139/398 st92f124/f150/f250 - external memory interface (extmi) 8.2 external memory signals the access to external memory is made using the as , ds , rw , port 0, port1, port9, ds2 and wait signals described below. refer to figure 71 . 8.2.1 as : address strobe as (output, active low, tristate) is active during the system clock high-level phase of each t1 memory cycle: an as rising edge indicates that memory address and read/write memory control signals are valid. a s is released in high-impedance during the bus acknowledge cycle or under the processor control by setting the himp bit (moder.0, r235). under reset, as is held high with an internal weak pull-up. the behavior of this signal is also affected by the bsz bit (st92f150d only), mc, asaf, eto, las[1:0] and uas[1:0] bits in the emr1 or emr2 registers. refer to the register description. 8.2.2 ds : data strobe ds (output, active low, tristate) is active during the internal clock high-level phase of each t2 memory cycle. during an external memory read cycle, the data on port 0 must be valid before the ds rising edge. during an external memory write cycle, the data on port 0 are output on the falling edge of ds and they are valid on the rising edge of ds . when the internal memory is accessed ds is kept high during the whole memory cycle. d s is released in high-impedance during bus ac- knowledge cycle or under processor control by set- ting the himp bit (moder.0, r235). under reset status, ds is held high with an internal weak pull-up. the behavior of this signal is also affected by the bsz bit (st92f150d only), lds[2:0], uds[2:0], ds2en and mc bit in the emr1 or wcr register. refer to the register description. 8.2.3 rw : read/write rw (output, active low, tristate) identifies the type of memory cycle: rw =1 identifies a memory read cycle, rw =0 identifies a memory write cy- cle. it is defined at the beginning of each memory cycle and it remains stable until the following memory cycle. rw is released in high-impedance during bus ac- knowledge cycle or under processor control by setting the himp bit (moder). under reset status, rw is held high with an inter- nal weak pull-up. the behavior of this signal is affected by the bsz bit (st92f150d only), mc and eto bits in the emr1 register. refer to the register description. 8.2.4 ds2 : data strobe 2 this additional data strobe pin (alternate function output, active low, tristate) allows two different external memories to be connected to the st9, the upper memory block (a21=1 typically ram) and the lower memory block (a21=0 typically rom) without any external logic. the selection between the upper and lower memory blocks depends on the a21 address pin value. the upper memory block is controlled by the ds pin while the lower memory block is controlled by the ds2 pin. when the internal memory is ad- dressed, ds2 is kept high during the whole mem- ory cycle. ds2 is enabled via software as the alter- nate function output of the associated i/o port bit. d s2 is released in high-impedance during bus ac- knowledge cycle or under processor control by setting the himp bit (moder.0, r235). the behavior of this signal is also affected by the bsz bit (st92f150d only) and the ds2en bit in the emr1 register. refer to the register descrip- tion. 9
140/398 st92f124/f150/f250 - external memory interface (extmi) external memory signals (contd) 8.2.5 port 0 if port 0 is used as a bit programmable parallel i/o port, it has the same features as a regular port. when set as an alternate function, it is used as the external memory interface: it outputs the mul- tiplexed address (8 lsb: a[7:0]) / data bus d[7:0]. 8.2.6 port 1 if port 1 is used as a bit programmable parallel i/o port, it has the same features as a regular port. when set as an alternate function, it is used as the external memory interface to provide the ad- dress bits a[15:8]. 8.2.7 port 9 [7:2] if port 9 is available and used as a bit programma- ble i/o port, it has the same features as a regular port. if the mmu is available on the device and port 9 is set as an alternate function, port 9[7:2] is used as the external memory interface to provide the 6 msb of the address (a[21:16]). note: for the st92f250 device, since a[18:17] share the same pins as sda1 and scl1 of i2c_1, these address bits are not available when the i2c_1 is in use (when i2ccr.pe bit is set). figure 70. application example ram 2 mbytes g e a[20:0] a[20:8] st9 ds p9[6:2], p1 q[7:0] p0 w rw d[7:0] as oe le q[7:0] d[7:0] latch a21 ds q[7:0] a[20:0] e rom 2 mbytes p9.7 a[7:0] 9
141/398 st92f124/f150/f250 - external memory interface (extmi) external memory signals (contd) figure 71. external memory read/write with a programmable wait as stretch ds stretch address address address address data in data in data out data t1 t2 t1 t2 twa twd no wait cycle 1 as wait cycle 1 ds wait cycle always read write as (mc=0) ale (mc=1) ds (mc=0) p0 rw (mc=0) oen (mc=1) wen (mc=1) p0 rw (mc=0) oen (mc=1) wen (mc=1) address address tavqv tavwh tavwl system clock (as pin) (ds pin) (rw pin) (ds pin) (rw pin) p1, p9 9
142/398 st92f124/f150/f250 - external memory interface (extmi) external memory signals (contd) figure 72. effects of ds2en on the behavior of ds and ds2 n ds stretch t1 t2 t1 t2 no wait cycle 1 ds wait cycle system as (mc=0) ds2en=0 or (ds2en=1 and upper memory addressed): ds2en=1 and lower memory addressed: ds oen oen ds2 (mc=1, read) (mc=1, write) (mc=0) oen ds2 (mc=0) oen2 (mc=1, read) oen2 (mc=1, write) clock oen2 (mc=1) (mc=0) (mc=1, read) (mc=1, write) ds (mc=0) (mc=1) ale (mc=1) 9
143/398 st92f124/f150/f250 - external memory interface (extmi) external memory signals (contd) 8.2.8 wait : external memory wait wait (alternate function input, active low) indi- cates to the st9 that the external memory requires more time to complete the memory access cycle. if bit ewen (eivr) is set, the wait signal is sam- pled with the rising edge of the processor internal clock during phase t1 or t2 of every memory cy- cle. if the signal was sampled active, one more in- ternal clock cycle is added to the memory cycle. on the rising edge of the added internal clock cy- cle, wait is sampled again to continue or finish the memory cycle stretching. note that if wait is sampled active during phase t1 then as is stretched, while if wait is sampled active during phase t2 then ds is stretched. wait is enabled via software as the alternate function input of the associated i/o port bit (refer to specific st9 ver- sion to identify the specific port and pin). refer to figure 73 . figure 73. external memory read/write sequence with external wait request (wait pin) t1 t2 t1 t2 always read write system as (mc=0) ale (mc=1) ds (mc=0) p0 rw (mc=0) oen (mc=1) wen (mc=1) p0 rw (mc=0) oen (mc=1) wen (mc=1) wait p1, p9 t1 t2 address add. add. add. d.out address d.out add. data out d.in d.in d.in address address address clock 9
144/398 st92f124/f150/f250 - external memory interface (extmi) 8.3 register description external memory register 1 (emr1) r245 - read/write register page: 21 reset value: 1000 0000 (80h) bit 7 = reserved. bit 6 = mc : mode control . 0: as , ds and rw pins have the standard st9 for- mat. 1: as pin becomes ale, address load enable. this signal indicates to the external address latch that a valid address is put on ad[7:0]. when ale is high, the multiplexed address/data bus ad[7:0] carries the lsbs of the memory ad- dress, which must be latched on the falling edge of this signal. ds becomes oen , output enable: when this signal is low, the external memory should put the data on the multiplexed address/data bus ad[7:0]. the data is sampled by the microcon- troller on the rising edge of the oen signal. rw pin becomes wen , write enable: when this signal is low, the multiplexed address/data bus ad[7:0] carries the data to be written in the ex- ternal memory. the external memory should sample the data on the rising edge of the wen signal. bit 5 = ds2en : data strobe 2 enable . 0: the ds pin is active for any external memory access (lower and upper memory block). the ds2 pin remains high. 1: if the lower memory block is addressed, the ds2 pin outputs the standard ds signal, while the ds pin stays high during the whole memory cycle. if the upper memory block is addressed, ds2 is forced to 1 during the whole memory cycle. refer to figure 72 bit 4 = asaf : address strobe as alternate func- tion. depending on the device, as can be either a ded- icated pin or a port alternate function. this bit is used only in the second case. 0: as alternate function disabled. 1: as alternate function enabled. bit 3 = reserved, must be kept cleared. bit 2 = eto : external toggle. 0: the external memory interface pins (as , ds , ds2 , rw , port0, port1, port9) toggle only if an access to external memory is performed. 1: when the internal memory protection is dis- abled (mask option), the above pins (except ds which never toggles during internal memory ac- cesses) toggle during both internal and external memory accesses. bit 1 = bsz : bus size. 0: all outputs use the standard low-noise output buffers. 1: p4[7:6], p6[5:4] use high-drive output buffers (on st92f150d, all i/o ports and a s , ds , and rw ). bit 0 = reserved. caution: external memory must be correctly ad- dressed before and after a write operation on the emr1 register. for example, if code is fetched from external memory using the standard st9 ex- ternal memory interface configuration (mc=0), setting the mc bit will cause the device to behave unpredictably. 70 x mc ds2en asaf 0 eto bsz x 9
145/398 st92f124/f150/f250 - external memory interface (extmi) external memory interface registers (contd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0001 1111 (1fh) bit 7 = reserved. bit 6 = encsr : enable code segment register. this bit affects the st9 cpu behavior whenever an interrupt request is issued. 0: the cpu works in original st9 compatibility mode concerning stack frame during interrupts. for the duration of the interrupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. the drawback is that it is not possible for an interrupt service routine to per- form inter-segment calls or jumps: these instruc- tions would update the csr, which, in this case, is not used (isr is used instead). the code seg- ment size for all interrupt service routines is thus limited to 64k bytes. 1: if encsr is set, isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also re- store csr from the stack. this approach allows interrupt service routines to access the entire 4mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. bit 5 = dprrem : data page registers remapping 0: the locations of the four mmu (memory man- agement unit) data page registers (dpr0, dpr1, dpr2 and dpr3) are in page 21. 1: the four mmu data page registers are swapped with that of the data registers of ports 0-3. refer to figure 69 bit 4 = memsel : memory selection. warning: must be kept at 1 . bit 3:2 = las[1:0] : lower memory address strobe stretch . these two bits contain the number of wait cycles (from 0 to 3) to add to the system clock to stretch as during external lower memory block accesses (a21=0). the reset value is 3. 70 - encsr dprrem memsel las1 las0 uas1 uas0 9
146/398 st92f124/f150/f250 - external memory interface (extmi) external memory interface registers (contd) bit 1:0 = uas[1:0] : upper memory address strobe stretch . these two bits contain the number of wait cycles (from 0 to 3) to add to the system clock to stretch as during external upper memory block accesses (a21=1). the reset value is 3. caution : the emr2 register cannot be written during an interrupt service routine. wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 7 = reserved, forced by hardware to 0. bit 6 = wdgen : watchdog enable. for a description of this bit, refer to the timer/ watchdog chapter. caution : clearing this bit has the effect of setting the timer/watchdog to watchdog mode. unless this is desired, it must be set to 1. bit 5:3 = uds[2:0] : upper memory data strobe stretch. these bits contain the number of intclk cycles to be added automatically to ds for external upper memory block accesses. uds = 0 adds no addi- tional wait cycles. uds = 7 adds the maximum 7 intclk cycles (reset condition). bit 2:0 = lds[2:0] : lower memory data strobe stretch. these bits contain the number of intclk cycles to be added automatically to ds for external lower memory block accesses. lds = 0 adds no addi- tional wait cycles, lds = 7 adds the maximum 7 intclk cycles (reset condition). note 1: the number of clock cycles added refers to intclk and not to cpuclk. note 2: the distinction between the upper memo- ry block and the lower memory block allows differ- ent wait cycles between the first 2 mbytes and the second 2 mbytes, and allows 2 different data strobe signals to be used to access 2 different memories. typically, the ram will be located above address 0x200000 and the rom below address 0x1fffff, with different access times (see figure 70 ). caution : the reset value of the wait control reg- ister gives the maximum number of wait cycles for external memory. to get optimum performance from the st9, the user should write the uds[2:0] and lds[2:0] bits to 0, if the external addressed memories are fast enough. 70 0 wdgen uds2 uds1 uds0 lds2 lds1 lds0 9
147/398 st92f124/f150/f250 - i/o ports 9 i/o ports 9.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). depending on the specific port, input buffers are software selectable to be ttl or cmos compatible, however on sch- mitt trigger ports, no selection is possible. 9.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 9.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 74 . port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or accumulator locations. figure 74. i/o register map group e group f page 2 group f page 3 group f page 43 system registers ffh reserved p7dr p9dr r255 feh p3c2 p7c2 p9c2 r254 fdh p3c1 p7c1 p9c1 r253 fch p3c0 p7c0 p9c0 r252 fbh reserved p6dr p8dr r251 fah p2c2 p6c2 p8c2 r250 f9h p2c1 p6c1 p8c1 r249 f8h p2c0 p6c0 p8c0 r248 f7h reserved reserved reserved r247 f6h p1c2 p5c2 r246 e5h p5dr r229 f5h p1c1 p5c1 r245 e4h p4dr r228 f4h p1c0 p5c0 r244 e3h p3dr r227 f3h reserved reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240 9
148/398 st92f124/f150/f250 - i/o ports port control registers (contd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 9.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 75 ) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit. this option is not available on schmitt trigger ports. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 9.5 alter- nate function architecture). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 76 . independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 77 ). C the output buffer is forced tristate. C the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. C the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin. 9
149/398 st92f124/f150/f250 - i/o ports input/output bit configuration (contd) figure 75. control bits n table 33. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) cmos (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input 9
150/398 st92f124/f150/f250 - i/o ports input/output bit configuration (contd) figure 76. basic structure of an i/o port pin figure 77. input configuration n n figure 78. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts 9
151/398 st92f124/f150/f250 - i/o ports input/output bit configuration (contd) when px.n is programmed as an output : ( figure 78 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : ( figure 79 ) C the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithme- tic/logic and boolean instructions performed on a bidirectional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : ( figure 80 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 79. bidirectional configuration n n figure 80. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch 9
152/398 st92f124/f150/f250 - i/o ports 9.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: C data bus input/output C alternate function input C alternate function output 9.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 9.5.2 pin declared as an alternate function input a single pin may be directly connected to several alternate function inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is re- quired to enable an alternate function input, since the input buffer is directly connected to each alter- nate function module on the shared pin. as more than one module can use the same input, it is up to the user software to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is perma- nently assigned by hardware as an a/d bit. in this case , after software programming of the bit in af- od-ttl, the alternate function output is forced to logic level 1. the analog voltage level on the cor- responding pin is directly input to the a/d (see fig- ure 81 ). figure 81. a/d input configuration 9.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 9.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. * depending on device input latch internal data bus i/o pin tristate input buffer output slave latch output master latch towards adc converter gnd mode ext. mem - i/o ports i/o ports p0 p1, p2, p6, p9[7:2] * wfi high imped- ance or next address (depending on the last memory op- eration per- formed on port) next address not affected (clock outputs running) halt high imped- ance next address not affected (clock outputs stopped) reset alternate function push- pull (romless device) bidirectional weak pull-up (high im- pedance when dis- abled in hardware). 9
153/398 timer/watchdog (wdt) 10 on-chip peripherals 10.1 timer/watchdog (wdt) important note: this chapter is a generic descrip- tion of the wdt peripheral. however depending on the st9 device, some or all of wdt interface signals described may not be connected to exter- nal pins. for the list of wdt pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 10.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: C generate periodic interrupts C measure input signal pulse widths C request an interrupt after a set number of events C generate an output signal waveform C act as a watchdog timer to monitor system in- tegrity the main wdt registers are: C control register for the input, output and interrupt logic blocks (wdtcr) C 16-bit counter register pair (wdthr, wdtlr) C prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: C wdin external clock input C wdout square wave or pwm signal output C int0 external interrupt input C nmi non-maskable interrupt input C hw0sw1 hardware/software watchdog ena- ble. figure 82. timer/watchdog block diagram int0 input & clock control logic inen inmd1 inmd2 wdtpr 8-bit prescaler wdtrh, wdtrl 16-bit intclk/4 wdt outmd wrout output control logic interrupt control logic end of count reset top level interrupt request outen mux wdout iaos tlis inta0 request nmi wdgen hw0sw1 wdin mux downcounter clock 9
154/398 timer/watchdog (wdt) timer/watchdog (contd) 10.1.2 functional description 10.1.2.1 external signals the hw0sw1 pin can be used to permanently en- able watchdog mode. refer to section 10.1.3.1 on page 155 . the wdin input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the wdout output pin can be used to generate a square wave or a pulse width modulated signal. an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter can be driven either by an external clock, or internally by intclk divided by 4. 10.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 10.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 10.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 10.1.2.5 input section if the timer/counter input is enabled (inen bit) it can count pulses input on the wdin pin. other- wise it counts the internal clock/4. for instance, when intclk = 24mhz, the end of count rate is: 2.79 seconds for maximum count (timer const. = ffffh, prescaler const. = ffh) 166 ns for minimum count (timer const. = 0000h, prescaler const. = 00h) the input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the mode is configurable in the wdtcr. 10.1.2.6 event counter mode in this mode the timer is driven by the external clock applied to the input pin, thus operating as an event counter. the event is defined as a high to low transition of the input signal. spacing between trailing edges should be at least 8 intclk periods (or 333ns with intclk = 24mhz). counting starts at the next input event after the st_sp bit is set and stops when the st_sp bit is reset. 9
155/398 timer/watchdog (wdt) timer/watchdog (contd) 10.1.2.7 gated input mode this mode can be used for pulse width measure- ment. the timer is clocked by intclk/4, and is started and stopped by means of the input pin and the st_sp bit. when the input pin is high, the tim- er counts. when it is low, counting stops. the maximum input pin frequency is equivalent to intclk/8. 10.1.2.8 triggerable input mode the timer (clocked internally by intclk/4) is started by the following sequence: C setting the start-stop bit, followed by C a high to low transition on the input pin. to stop the timer, reset the st_sp bit. 10.1.2.9 retriggerable input mode in this mode, the timer (clocked internally by intclk/4) is started by setting the st_sp bit. a high to low transition on the input pin causes counting to restart from the initial value. when the timer is stopped (st_sp bit reset), a high to low transition of the input pin has no effect. 10.1.2.10 timer/counter output modes output modes are selected by means of the out- en (output enable) and outmd (output mode) bits of the wdtcr register. no output mode (outen = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outen = 1, outmd = 0) the timer outputs a signal with a frequency equal to half the end of count repetition rate on the wd- out pin. with an intclk frequency of 20mhz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. pulse width modulated output mode (outen = 1, outmd = 1) the state of the wrout bit is transferred to the output pin (wdout) at the end of count, and is held until the next end of count condition. the user can thus generate pwm signals by modifying the status of the wrout pin between end of count events, based on software counters decre- mented by the timer watchdog interrupt. 10.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 10.1.3.1 hardware watchdog/software watchdog the hw0sw1 pin (when available) selects hard- ware watchdog or software watchdog. if hw0sw1 is held low: C the watchdog is enabled by hardware immedi- ately after an external reset. (note: software re- set or watchdog reset have no effect on the watchdog enable status). C the initial counter value (ffffh) cannot be mod- ified, however software can change the prescaler value on the fly. C the wdgen bit has no effect. (note: it is not forced low). if hw0sw1 is held high, or is not present: C the watchdog can be enabled by resetting the wdgen bit. 10.1.3.2 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated. 9
156/398 timer/watchdog (wdt) timer/watchdog (contd) 10.1.3.3 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 10.1.3.4 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp, s_c and the input mode selection bits are ignored. hence, regard- less of their status, the counter always runs in continuous mode, driven by the internal clock. the output mode should not be enabled, since in this context it is meaningless. figure 83. watchdog timer mode timer start counting wri te wdtrh,wdtrl wd en=0 write aah,55h into wdtrl reset software fail (e.g. infinite loop) or peripheral fail va00220 produce count reload value count g 9
157/398 timer/watchdog (wdt) timer/watchdog (contd) 10.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 84 . note: software traps can be generated by setting the appropriate interrupt pending bit. table 34 below, shows all the possible configura- tions of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters . figure 84. interrupt sources table 34. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watchdog reset wdgen (wcr.6) inta0 request ia0s (eivr.1) mux 0 1 int0 mux 0 1 top level interrupt request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer 9
158/398 timer/watchdog (wdt) timer/watchdog (contd) 10.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note : the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16-bit register (wdtlr, wdthr) is used to load the 16-bit counter value. the registers can be read or written on the fly. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = r[15:8] counter most significant bits . timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) bits 7:0 = r[7:0] counter least significant bits. timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h) bit 7 = st_sp : start/stop bit . this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c : single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection bits . these bits select the input mode: 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c inmd1 inmd2 inen outmd wrout outen inmd1 inmd2 input mode 0 0 event counter 0 1 gated input (reset value) 1 0 triggerable input 1 1 retriggerable input 9
159/398 timer/watchdog (wdt) timer/watchdog (contd) bit 3 = inen : input enable . this bit is set and cleared by software. 0: disable input section 1: enable input section bit 2 = outmd : output mode. this bit is set and cleared by software. 0: the output is toggled at every end of count 1: the value of the wrout bit is transferred to the output pin on every end of count if outen=1. bit 1 = wrout : write out . the status of this bit is transferred to the output pin when outmd is set; it is user definable to al- low pwm output (on reset wrout is set). bit 0 = outen : output enable bit . this bit is set and cleared by software. 0: disable output 1: enable output wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set any more by the user program. at system reset, the watch- dog mode is disabled. note: this bit is ignored if the hardware watchdog option is enabled by pin hw0sw1 (if available). external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source warning : to avoid spurious interrupt requests, the ia0s bit should be accessed only when the in- terrupt logic is disabled (i.e. after the di instruc- tion). it is also necessary to clear any possible in- terrupt pending requests on channel a0 before en- abling this interrupt channel. a delay instruction (e.g. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ia0s write instruction. other bits are described in the interrupt section. 70 xwdgenxxxxxx 70 x x x x x tlis ia0s x 9
160/398 standard timer (stim) 10.2 standard timer (stim) important note: this chapter is a generic descrip- tion of the stim peripheral. depending on the st9 device, some or all of the interface signals de- scribed may not be connected to external pins. for the list of stim pins present on the particular st9 device, refer to the pinout description in the first section of the data sheet. 10.2.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer uses an input pin (stin) and an output (stout) pin. these pins, when available, may be independent pins or connected as alternate functions of an i/o port bit. stin can be used in one of four programmable in- put modes: C event counter, C gated external input mode, C triggerable input mode, C retriggerable input mode. stout can be used to generate a square wave or pulse width modulated signal. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler can be driven either by an internal clock equal to intclk divided by 4, or by clock2 derived directly from the external oscilla- tor, divided by device dependent prescaler value, thus providing a stable time reference independ- ent from the pll programming or by an external clock connected to the stin pin. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 85. standard timer block diagram n stout 1 external input & clock control logic inen inmd1 inmd2 stp 8-bit prescaler sth,stl 16-bit standard timer clock outmd1 outmd2 output control logic interrupt control logic end of count ints interrupt request clock2/x stin 1 interrupt 1 downcounter (see note 2) note 2: depending on device, the source of the input & clock control logic block may be permanently connected either to stin or the rccu signal clock2/x. in devices without stin and clock2, the intclk/4 mux note 1: pin not present on all st9 devices . inen bit must be held at 0. 9
161/398 standard timer (stim) standard timer (contd) 10.2.2 functional description 10.2.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standard timer, the prescaler (stp) and counter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. it is only stopped by resetting the start/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 10.2.2.2 standard timer input modes (st9 devices with standard timer input stin) bits inmd2, inmd1 and inen are used to select the input modes. the input enable (inen) bit ena- bles the input mode selected by the inmd2 and inmd1 bits. if the input is disabled (inen="0"), the values of inmd2 and inmd1 are not taken into ac- count. in this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by intclk/4 and transitions on the input pin have no effect. event counter mode (inmd1 = "0", inmd2 = "0") the standard timer is driven by the signal applied to the input pin (stin) which acts as an external clock. the unit works therefore as an event coun- ter. the event is a high to low transition on stin. spacing between trailing edges should be at least the period of intclk multiplied by 8 (i.e. the max- imum standard timer input frequency is 3 mhz with intclk = 24mhz). gated input mode (inmd1 = "0", inmd2 = 1) the timer uses the internal clock (intclk divided by 4) and starts and stops the timer according to the state of stin pin. when the status of the stin is high the standard timer count operation pro- ceeds, and when low, counting is stopped. triggerable input mode (inmd1 = 1, inmd2 = 0) the standard timer is started by: a) setting the start-stop bit, and b) a high to low (low trigger) transition on stin. in order to stop the standard timer in this mode, it is only necessary to reset the start-stop bit. retriggerable input mode (inmd1 = 1, inmd2 = 1) in this mode, when the standard timer is running (with internal clock), a high to low transition on stin causes the counting to start from the last constant loaded into the stl/sth and stp regis- ters. when the standard timer is stopped (st-sp bit equal to zero), a high to low transition on stin has no effect. 10.2.2.3 time base generator (st9 devices without standard timer input stin) for devices where stin is replaced by a connec- tion to clock2, the condition (inmd1 = 0, inmd2 = 0) will allow the standard timer to gen- erate a stable time base independent from the pll programming. 9
162/398 standard timer (stim) standard timer (contd) 10.2.2.4 standard timer output modes output modes are selected using 2 bits of the stc register: outmd1 and outmd2. no output mode (outmd1 = 0, outmd2 = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outmd1 = 0, outmd2 = 1) the standard timer toggles the state of the stout pin on every end of count condition. with intclk = 24mhz, this allows generation of a square wave with a period ranging from 333ns to 5.59 seconds. pwm output mode (outmd1 = 1) the value of the outmd2 bit is transferred to the stout output pin at the end of count. this al- lows the user to generate pwm signals, by modi- fying the status of outmd2 between end of count events, based on software counters decremented on the standard timer interrupt. 10.2.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to 1, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 10.2.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. note: the four standard timers are not implement- ed on all st9 devices. refer to the block diagram of the device for the number of timers. std timer register register address stim0 sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h) stim1 sth1 r244 (f4h) stl1 r245 (f5h) stp1 r246 (f6h) stc1 r247 (f7h) stim2 sth2 r248 (f8h) stl2 r249 (f9h) stp2 r250 (fah) stc2 r251 (fbh) stim3 sth3 r252 (fch) stl3 r253 (fdh) stp3 r254 (feh) stc3 r255 (ffh) 9
163/398 standard timer (stim) standard timer (contd) 10.2.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[15:8] : counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counters current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp : start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c : single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection. these bits select the input functions as shown in section 10.2.2.2 , when enabled by inen. bit 3 = inen : input enable. this bit is set and cleared by software. if neither the stin pin nor the clock2 line are present, inen must be 0. 0: input section disabled 1: input section enabled bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bits 1:0 = outmd[1:2] : output mode selection. these bits select the output functions as described in section 10.2.2.4 . 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st - sp s-c inmd1 inmd2 inen ints outmd1 outmd2 inmd1 inmd2 mode 00 event counter mode 01 gated input mode 10 triggerable mode 11 retriggerable mode outmd1 outmd2 mode 00 no output mode 01 square wave output mode 1x pwm output mode 9
164/398 extended function timer (eft) 10.3 extended function timer (eft) 10.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the intclk prescaler. 10.3.2 main features n programmable prescaler: intclk divided by 2, 4 or 8. n overflow status flag and maskable interrupts n external clock input (must be at least 4 times slower than the intclk clock speed) with the choice of active edge n output compare functions with C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C maskable interrupt generation n input capture functions with C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C maskable interrupt generation n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports n global timer interrupt (efti). the block diagram is shown in figure 86 . table 35. eft pin naming conventions 10.3.3 functional description 10.3.3.1 counter the principal block of the programmable timer is a 16-bit free running counter and its associated 16-bit registers: counter registers C counter high register (chr) is the most sig- nificant byte (msb). C counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers C alternate counter high register (achr) is the most significant byte (msb). C alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note page 166 ). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 36 . the value in the counter register repeats every 131.072, 262.144 or 524.288 intclk cycles de- pending on the cc[1:0] bits. function eft0 eft1 input capture 1 - icap1 icapa0 icapa1 input capture 2 - icap2 icapb0 icapb1 output compare 1 - ocmp1 ocmpa0 ocmpa1 output compare 2 - ocmp2 ocmpb0 ocmpb1 9
165/398 extended function timer (eft) extended function timer (contd) figure 86. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st9 internal bus latch1 ocmp1 icap1 extclk intclk efti interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter oc2ie ic1ie eftis - - - oc1ie ic2ie cr3 10 ocf2 ocf1 icf2 icf1 10 request 1 0 intx external interrupt pin 9
166/398 extended function timer (eft) extended function timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set C eftis bit of the cr3 register is set. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done by: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the reset count (mcu awakened by a reset). 10.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin ext- clk that will trigger the free running counter. the counter is synchronised with the falling edge of intclk. at least four falling edges of the intclk must oc- cur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the intclk fre- quency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed 9
167/398 extended function timer (eft) extended function timer (contd) figure 87. counter timing diagram, intclk divided by 2 figure 88. counter timing diagram, intclk divided by 4 figure 89. counter timing diagram, intclk divided by 8 intclk fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 intclk internal reset timer clock counter register overflow flag tof intclk internal reset timer clock counter register overflow flag tof fffc fffd 0000 9
168/398 extended function timer (eft) extended function timer (contd) 10.3.3.3 input capture in this section, the index, i , may be 1 or 2. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i rregister is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( intclk /cc[1:0] ). procedure to use the input capture function select the follow- ing in the cr2 register: C select the timer clock (cc[1:0] (see table 36 ). C select the edge of the active transition on the icap2 pin with the iedg2 bit, if icap2 is active. and select the following in the cr1/cr3 register: C to enable both icap1 & icap2 interrupts, set the icie bit in the cr1 register (in this case, the ic1ie & ic2ie enable bits are not significant). to enable only one icap interrupt, reset the icie bit and set the ic1ie (or ic2ie) bit. note: if icie is reset and both ic1ie & ic2ie are set, both interrupts are enabled. in all cases, set the eftis bit to enable timer in- terrupts globally C select the edge of the active transition on the icap1 pin with the iedg1 bit if icap1 is active. when an input capture occurs: C icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 91 ). C a timer interrupt is generated under the following two conditions : 1. if the icie bit (for both icap1 & icap2) and the eftis bit are set. note: if the icie bit is set, the status of the ic1ie/ic2ie bits in the cr3 register is not sig- nificant. 2. if the icie bit is reset and the ic1ie and /or ic2ie bits are set and the eftis bit is set. otherwise, the interrupt remains pending until the related enable bits are set. clearing the input capture interrupt request is done by: 1. an access (read or write) to the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: after reading the ic i hr register, transfer of input capture data is inhibited until the ic i lr regis- ter is also read. the ic i r register always contains the free running counter value which corresponds to the most re- cent input capture. ms byte ls byte ic i ric i hr ic i lr 9
169/398 extended function timer (eft) extended function timer (contd) figure 90. input capture block diagram figure 91. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r ic2r edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. 9
170/398 extended function timer (eft) extended function timer (contd) 10.3.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( intclk / cc[1:0] ). procedure to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed, the oc- mp i pin is then dedicated to the output compare function. C select the timer clock (cc[1:0] see table 36 ). select the following in the cr1/cr3 register: C select the olvl i bit to be applied to the ocmp pins after the match occurs. C to enable both ocmp1 & ocmp2 interrupts, set the ocie bit in the cr1 register (in this case, the oc1ie & oc2ie enable bits are not significant). to enable only one ocmp interrupt, reset the ocie bit and set the oc1ie (or oc2ie) bit. note: if ocie is reset and both oc1ie & oc2ie are set, both interrupts are enabled. in all cases, set the eftis bit to enable timer in- terrupts globally. when a match is found: C the ocf i bit is set. C the ocmp i pin takes the olvl i bit value (the ocmp i pin latch is forced low during reset and stays low until a valid compare changes it to the olvl i level). C a timer interrupt is generated under the following two conditions : 1. if the ocie bit (for both ocmp1 & ocmp2) and the eftis bit are set. note: if the ocie bit is set, the status of the oc1ie/oc2ie bits in the cr3 register is not significant. 2. if the ocie bit is reset and the oc1ie and /or oc2ie bits are set and the eftis bit is set. otherwise, the interrupt remains pending until the related enable bits are set. clearing the output compare interrupt request is done by: C an access (read or write) to the sr register while the ocf i bit is set. C an access (read or write) to the oc i lr register. note: after a write access to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. if the oc i e bit is not set, the ocmp i pin is a gen- eral i/o port and the olvl i bit will not appear when match is found but an interrupt could be gen- erated if the ocie bit is set. the value in the 16-bit oc i r register and the olvl i bit should be changed after each success- ful comparison in order to control an output wave- form or establish a new elapsed timeout. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = desired output compare period (in seconds) intclk = internal clock frequency cc[1:0] = timer clock prescaler the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * intclk (cc1.cc0) 9
171/398 extended function timer (eft) extended function timer (contd) figure 92. output compare block diagram figure 93. output compare timing diagram, internal clock divided by 2 output compare 16-bit circuit oc1r 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r intclk timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc 9
172/398 extended function timer (eft) extended function timer (contd) 10.3.3.5 forced compare mode in this section i may represent 1 or 2. the following bits of the cr1 register are used: when the folv1 bit is set, the olvl1 bit is copied to the ocmp1 pin if pwm and opm are both cleared. when the folv2 bit is set, the olvl2 bit is copied to the ocmp2 pin. the olv li bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). notes: C the ocf i bit is not set when folvi is set, and thus no interrupt request is generated. C the ocfi bit can be set if oc i r = counter and an interrupt can be generated if enabled. this can be avoided by writing in the oc i hr register. the output compare function is inhibited till oc i lr is also written. C the input capture function works in forced com- pare mode. to disable it, read the ic i hr register. input capture will be inhibited till ic i lr is read. 10.3.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode, select the following in the the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit . and select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then dedi- cated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 36 ). load the oc1r register with the value corre- sponding to the length of the pulse (see the formu- la in section 10.3.3.7 ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin. when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 94 ). notes: C the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. C the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set or icie is reset and ic1ie is set. the ic1r regis- ter will have the value fffch. C when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. C when one pulse mode (opm) and forced com- pare 1 mode (folv1) bits are set then opm is the active mode C forced compare 2 mode works in opm C input capture 2 function works in opm C when oc1r = fffch in opm, then a pulse of width fffch is generated C if ic1hr register is read in opm before an active edge of icap1, then opm is inhibited till ic1lr is also read. folv2 folv1 olvl2 olvl1 event occurs counter is initialized to fffch ocmp1 = olvl2 counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle 9
173/398 extended function timer (eft) extended function timer (contd) C if an event occurs on icap1 again before the counter reaches the oc1r value, then the counter will be reset again and the pulse gener- ated might be longer than expected as in figure 94 . C if a write operation is performed on clr or aclr register before the counter reaches the oc1r value, then the counter will be reset again and the pulse generated might be longer than expect- ed. figure 94. one pulse mode timing counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 0010 fffc 9
174/398 extended function timer (eft) extended function timer (contd) 10.3.3.7 pulse width modulation mode pulse width modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register. procedure to use pulse width modulation mode select the fol- lowing in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with oc2r register. and select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. C set the pwm bit. C select the timer clock cc[1:0] bits (see table 36 ). load the oc2r register with the value corre- sponding to the period of the signal. load the oc1r register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). if olvl1=1 and olvl2=0 the length of the pulse is the difference between the oc2r and oc1r registers. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: C t = desired output compare period (seconds) C intclk = internal clock frequency C cc1-cc0 = timer clock prescaler the output compare 2 event causes the counter to be initialized to fffch (see figure 95 ). notes: C after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. C the ocf1 bit cannot be set by hardware in pwm mode, but the ocf2 bit is set every time the counter matches the oc2r register. C the input capture function is available in pwm mode. C when counter = oc2r, then the ocf2 bit will be set. this can generate an interrupt if ocie is set or ocie is reset and oc2ie is set. this interrupt is useful in applications where the pulse-width or period needs to be changed interactively. C when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active mode. C the value loaded in register oc2r must always be greater than the value in register oc1r in or- der to produce meaningful waveforms. note that 0000h is considerred to be greater than fffch or fffdh or fffeh or ffffh. C when oc1r >oc2r, no waveform will be gen- erated. C when oc2r = oc1r, a square waveform will be generated as in figure 95 C when oc2r is loaded with fffc (the counter reset value) then no waveform will be generated & the counter will remain stuck at fffc. C when oc1r is loaded with fffc (the counter reset value) then the waveform will be generated as in figure 95 C when folv1 bit is set and pwm bit is set, then pwm mode is the active one. but if folv2 bit is set then the olvl2 bit will appear on ocmp2 (when oc2e bit = 1). oc i r value = t * intclk cc[1:0] - 5 counter counter is reset to fffch ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle 9
175/398 extended function timer (eft) extended function timer (contd) C when a write is performed on the clr or aclr register in pwm mode, then the counter will be reset and the pulse-width/period of the waveform generated may not be be as desired figure 95. pulse width modulation mode timing counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 counter 000f 0010 fffc 0010 fffc olvl1 olvl1 olvl2 ocmp1 oc1r = oc2r = 0010h, olvl1 = 1, olvl2 = 0 0010 fffc counter 0003 0004 fffc olvl1 olvl2 ocmp1 oc1r = fffch, oc2r = 0004h, olvl1 = 1, olvl2 = 0 0003 0004 fffc olvl1 olvl2 9
176/398 extended function timer (eft) extended function timer (contd) 10.3.4 interrupt management the interrupts of the extended function timer are mapped on one of the eight external interrupt channels of the microcontroller (refer to the inter- rupts chapter). the three interrupt sources are mapped on the same interrupt channel. to use them, the eftis bit must be set) each external interrupt channel has: C a trigger control bit in the eitr register (r242 - page 0), C a pending bit in the eipr register (r243 - page 0), C a mask bit in the eimr register (r244 - page 0). program the interrupt priority level using the ei- plr register (r245 - page 0). for a description of these registers refer to the interrupts and dma chapters. using the external interrupt channel for all eft interrupts to use the interrupt features, perform the following sequence: C set the priority level of the interrupt channel used (eiplr register) C select the interrupt trigger edge as rising edge (set the corresponding bit in the eitr register) C set the eftis bit of the cr3 register to select the peripheral interrupt sources C set the ocie (or oc1ie/oc2ie bits) and/or icie (or ic1ie/ic2ie bits and/or toie bit(s) in the cr1 register to enable interrupts C in the eipr register, reset the pending bit of the interrupt channel used by the peripheral inter- rupts to avoid any spurious interrupt requests be- ing performed when the mask bit is set C set the mask bits of the interrupt channels used to enable the mcu to acknowledge the interrupt requests of the peripheral. C clear all eft interrupt flags by reading the sta- tus, input capture low, output compare low and counter low registers. caution: 1. it is mandatory to clear all eft interrupt flags simultaneously at least once before exiting an eft timer interrupt routine (the sr register must = 00h at some point during the interrupt routine), otherwise no interrupts can be issued on that channel anymore. refer to the following assembly code for an interrupt sequence example. 2. since a loop statement is needed inside the it routine, the user must avoid situations where an interrupt event period is narrower than the duration of the interrupt treatment. otherwise nested interrupt mode must be used to serve higher priority requests. 9
177/398 extended function timer (eft) extended function timer (contd) note: a single access (read/write) to the sr regis- ter at the beginning of the interrupt routine is the first step needed to clear all the eft interrupt flags. in a second step, the lower bytes of the data registers must be accessed if the corresponding flag is set. it is not necessary to access the sr register between these instructions, but it can done. ; interrupt routine example push r234 ; save current page spp #28 ; set eft page l6: cp r254,#0 ; while e0_sr is not cleared jxz l7 tm r254,#128 ; check input capture 1 flag jxz l2 ; else go to next test ld r1,r241 ; dummy read to clear ic1lr ; insert your code here l2: tm r254,#16 ; check input capture 2 flag jxz l3 ; else go to next test ld r1,r243 ; dummy read to clear ic2lr ; insert your code here l3: tm r254,#64 ; check input compare 1 flag jxz l4 ; else go to next test ld r1,r249 ; dummy read to clear oc1lr ; insert your code here l4: tm r254,#8 ; check input compare 2 flag jxz l5 ; else go to next test ld r1,r251 ; dummy read to clear oc1lr ; insert your code here l5: tm r254,#32 ; check input overflow flag jxz l6 ; else go to next test ld r1,r245 ; dummy read to clear overflow flag ; insert your code here jx l6 l7: pop r234 ; restore current page iret 9
178/398 extended function timer (eft) extended function timer (contd) 10.3.5 register description each timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the counter and the alternate counter. notes: 1. in the register description on the following pag- es, register and page numbers are given using the example of timer 0. on devices with more than one timer, refer to the device register map for the adresses and page numbers. 2. to work correctly with register pairs, it is strong- ly recommended to use single byte instructions. do not use word instructions to access any of the 16-bit registers. input capture 1 high register (ic1hr) r240 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) r241 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). input capture 2 high register (ic2hr) r242 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) r243 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
179/398 extended function timer (eft) extended function timer (contd) counter high register (chr) r244 - read only register page: 28 reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) r245 - read/write register page: 28 reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) r246 - read only register page: 28 reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) r247 - read/write register page: 28 reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in the sr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
180/398 extended function timer (eft) extended function timer (contd) output compare 1 high register (oc1hr) r248 - read/write register page: 28 reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) r249 - read/write register page: 28 reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) r250 - read/write register page: 28 reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) r251 - read/write register page: 28 reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
181/398 extended function timer (eft) extended function timer (contd) control register 1 (cr1) r252 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt enabling depends on the ic1ie and ic2ie bits in the cr3 register. 1: an interrupt is generated whenever the icf1 or icf2 bit in the sr register is set. the ic1ie and ic2ie bits in the cr3 register do not have any effect in this case. bit 6 = ocie output compare interrupt enable. 0: interrupt generation depends on the oc1ie and oc2ie bits in the cr3 register. 1: an interrupt is generated whenever the ocf1 or ocf2 bit in the sr register is set. the oc1ie and oc2ie bits in the cr3 rgister do not have any effect in this case. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. 0: no effect. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. 0: no effect. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and oc2e is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 9
182/398 extended function timer (eft) extended function timer (contd) control register 2 (cr2) r253 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the value of the timer clock depends on these bits: table 36. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg cc1 cc0 timer clock 00 intclk / 4 01 intclk / 2 10 intclk / 8 1 1 external clock 9
183/398 extended function timer (eft) extended function timer (contd) status register (sr) r254 - read only register page: 28 reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2:0 = reserved, forced by hardware to 0. control register 3 (cr3) r255 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7 = ic1ie input capture1 interrupt enable this bit is not significant if the icie bit in the cr1 register is set. 0: icap1 interrupt disabled 1: icap1 interrupt enabled bit 6 = oc1ie output compare 1 interrupt enable this bit is not significant if the ocie bit in the cr1 register is set. 0: ocmp1 interrupt disabled 1: ocmp1 interrupt enabled bit 5 = ic2ie input capture 2 interrupt enable this bit is not significant if the icie bit in the cr1 register is set. 0: icap2 interrupt disabled 1: icap2 interrupt enabled bit 4= oc2ie output compare 2 interrupt enable this bit is not significant if the ocie bit in the cr1 register is set. 0: ocmp2 interrupt disabled 1: ocmp2 interrupt enabled bits 3:1 = reserved, must be kept cleared. bit 0 = eftis global timer interrupt selection. 0: select external interrupt. 1: select global timer interrupt. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 ic1ie oc1ie ic2ie oc2ie 0 0 0 eftis 9
184/398 extended function timer (eft) extended function timer (contd) table 37. extended function timer register map address (dec.) register name 76543210 r240 ic1hr reset value msb xxxxxxx lsb x r241 ic1lr reset value msb xxxxxxx lsb x r242 ic2hr reset value msb xxxxxxx lsb x r243 ic2lr reset value msb xxxxxxx lsb x r244 chr reset value msb 1111111 lsb 1 r245 clr reset value msb 1111110 lsb 0 r246 achr reset value msb 1111111 lsb 1 r247 aclr reset value msb 1111110 lsb 0 r248 oc1hr reset value msb 1000000 lsb 0 r249 oc1lr reset value msb 0000000 lsb 0 r250 oc2hr reset value msb 1000000 lsb 0 r251 oc2lr reset value msb 0000000 lsb 0 r252 cr1 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 r253 cr2 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 r254 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 r255 cr3 reset value ic1ie 0 oc1ie 0 ic2ie 0 oc2ie 0 - 0 - 0 - 0 eftis 0 9
185/398 multifunction timer (mft) 10.4 multifunction timer (mft) 10.4.1 introduction the multifunction timer (mft) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic pwm generation and frequency measurement. the mft comprises a 16-bit up/down counter driven by an 8-bit programmable prescaler. the in- put clock may be intclk/3 or an external source. the timer features two 16-bit comparison regis- ters, and two 16-bit capture/load/reload regis- ters. two input pins and two alternate function out- put pins are available. several functional configurations are possible, for instance: C 2 input captures on separate external lines, and 2 independent output compare functions with the counter in free-running mode, or 1 output com- pare at a fixed repetition rate. C 1 input capture, 1 counter reload and 2 inde- pendent output compares. C 2 alternate autoreloads and 2 independent out- put compares. C 2 alternate captures on the same external line and 2 independent output compares at a fixed repetition rate. when two mfts are present in an st9 device, a combined operating mode is available. an internal on-chip event signal can be used on some devices to control other on-chip peripherals. the two external inputs may be individually pro- grammed to detect any of the following: C rising edges C falling edges C both rising and falling edges figure 96. mft simplified block diagram 9
186/398 multifunction timer (mft) multifunction timer (contd) the configuration of each input is programmed in the input control register. each of the two output pins can be driven from any of three possible sources: C compare register 0 logic C compare register 1 logic C overflow/underflow logic each of these three sources can cause one of the following four actions, independently, on each of the two outputs: C nop, set, reset, toggle in addition, an additional on-chip event signal can be generated by two of the three sources men- tioned above, i.e. over/underflow event and com- pare 0 event. this signal can be used internally to synchronise another on-chip peripheral. five maskable interrupt sources referring to an end of count condition, 2 input captures and 2 output compares, can generate 3 different interrupt re- quests (with hardware fixed priority), pointing to 3 interrupt routine vectors. two independent dma channels are available for rapid data transfer operations. each dma request (associated with a capture on the reg0r register, or with a compare on the cmp0r register) has pri- ority over an interrupt request generated by the same source. a swap mode is also available to allow high speed continuous transfers (see interrupt and dma chapter). figure 97. detailed block diagram 9
187/398 multifunction timer (mft) multifunction timer (contd) 10.4.2 functional description the mft operating modes are selected by pro- gramming the timer control register (tcr) and the timer mode register (tmr). 10.4.2.1 trigger events a trigger event may be generated by software (by setting either the cp0 or the cp1 bits in the t_flagr register) or by an external source which may be programmed to respond to the rising edge, the falling edge or both by programming bits a0- a1 and b0-b1 in the t_icr register. this trigger event can be used to perform a capture or a load, depending on the timer mode (configured using the bits in table 41 ). an event on the txina input or setting the cp0 bit triggers a capture to, or a load from the reg0r register (except in bicapture mode, see section 10.4.2.11 ). an event on the txinb input or setting the cp1 bit triggers a capture to, or a load from the reg1r register. in addition, in the special case of "load from reg0r and monitor on reg1r", it is possible to use the txinb input as a trigger for reg0r." 10.4.2.2 one shot mode when the counter generates an overflow (in up- count mode), or an underflow (in down-count mode), that is to say when an end of count condi- tion is reached, the counter stops and no counter reload occurs. the counter may only be restarted by an external trigger on txina or b or a by soft- ware trigger on cp0 only. one shot mode is en- tered by setting the co bit in tmr. 10.4.2.3 continuous mode whenever the counter reaches an end of count condition, the counting sequence is automatically restarted and the counter is reloaded from reg0r (or from reg1r, when selected in biload mode). continuous mode is entered by resetting the c0 bit in tmr. 10.4.2.4 triggered and retriggered modes a triggered event may be generated by software (by setting either the cp0 or the cp1 bit in the t_flagr register), or by an external source which may be programmed to respond to the rising edge, the falling edge or both, by programming bits a0-a1 and b0-b1 in t_icr. in one shot and triggered mode, every trigger event arriving before an end of count, is masked. in one shot and retriggered mode, every trigger received while the counter is running, automatical- ly reloads the counter from reg0r. triggered/re- triggered mode is set by the ren bit in tmr. the txina input refers to reg0r and the txinb input refers to reg1r. warning . if the triggered mode is selected when the counter is in continuous mode, every trigger is disabled, it is not therefore possible to synchronise the counting cycle by hardware or software. 10.4.2.5 gated mode in this mode, counting takes place only when the external gate input is at a logic low level. the se- lection of txina or txinb as the gate input is made by programming the in0-in3 bits in t_icr. 10.4.2.6 capture mode the reg0r and reg1r registers may be inde- pendently set in capture mode by setting rm0 or rm1 in tmr, so that a capture of the current count value can be performed either on reg0r or on reg1r, initiated by software (by setting cp0 or cp1 in the t_flagr register) or by an event on the external input pins. warning . care should be taken when two soft- ware captures are to be performed on the same register. in this case, at least one instruction must be present between the first cp0/cp1 bit set and the subsequent cp0/cp1 bit reset instructions. 10.4.2.7 up/down mode the counter can count up or down depending on the state of the udc bit (up/down count) in tcr, or on the configuration of the external input pins, which have priority over udc (see input pin as- signment in t_icr). the udcs bit returns the counter up/down current status (see also the up/ down autodiscrimination mode in the input pin assignment section). 9
188/398 multifunction timer (mft) multifunction timer (contd) 10.4.2.8 free running mode the timer counts continuously (in up or down mode) and the counter value simply overflows or underflows through ffffh or zero; there is no end of count condition as such, and no reloading takes place. this mode is automatically selected either in bi-capture mode or by setting register reg0r for a capture function (continuous mode must also be set). in autoclear mode, free running operation can be selected, with the possibility of choosing a maximum count value less than 2 16 before overflow or underflow (see autoclear mode). 10.4.2.9 monitor mode when the rm1 bit in tmr is reset, and the timer is not in bi-value mode, reg1r acts as a monitor, duplicating the current up or down counter con- tents, thus allowing the counter to be read on the fly. 10.4.2.10 autoclear mode a clear command forces the counter either to 0000h or to ffffh, depending on whether up- counting or downcounting is selected. the counter reset may be obtained either directly, through the ccl bit in tcr, or by entering the autoclear mode, through the ccp0 and ccmp0 bits in tcr. every capture performed on reg0r (if ccp0 is set), or every successful compare performed by cmp0r (if ccmp0 is set), clears the counter and reloads the prescaler. the clear on capture mode allows direct meas- urement of delta time between successive cap- tures on reg0r, while the clear on compare mode allows free running with the possibility of choosing a maximum count value before overflow or underflow which is less than 2 16 (see free run- ning mode). 10.4.2.11 bi-value mode depending on the value of the rm0 bit in tmr, the bi-load mode (rm0 reset) or the bi-capture mode (rm0 set) can be selected as illustrated in figure 38 below: table 38. bi-value modes a) biload mode the bi-load mode is entered by selecting the bi- value mode (bm set in tmr) and programming reg0r as a reload register (rm0 reset in tmr). at any end of count, counter reloading is per- formed alternately from reg0r and reg1r, (a low level for bm bit always sets reg0r as the cur- rent register, so that, after a low to high transition of bm bit, the first reload is always from reg0r). tmr bits timer operating modes rm0 rm1 bm 0 1 x x 1 1 bi-load mode bi-capture mode 9
189/398 multifunction timer (mft) multifunction timer (contd) every software or external trigger event on reg0r performs a reload from reg0r resetting the biload cycle. in one shot mode (reload initiat- ed by software or by an external trigger), reloading is always from reg0r. b) bicapture mode the bicapture mode is entered by selecting the bi- value mode (the bm bit in tmr is set) and by pro- gramming reg0r as a capture register (the rm0 bit in tmr is set). interrupt generation can be configured as an and or or function of the two capture events. this is configured by the a0 bit in the t_flagr register. every capture event, software simulated (by set- ting the cp0 flag) or coming directly from the txi- na input line, captures the current counter value alternately into reg0r and reg1r. when the bm bit is reset, reg0r is the current register, so that the first capture, after resetting the bm bit, is always into reg0r. 10.4.2.12 parallel mode when two mfts are present on an st9 device, the parallel mode is entered when the eck bit in the tmr register of timer 1 is set. the timer 1 prescaler input is internally connected to the timer 0 prescaler output. timer 0 prescaler input is con- nected to the system clock line. by loading the prescaler register of timer 1 with the value 00h the two timers (timer 0 and timer 1) are driven by the same frequency in parallel mode. in this mode the clock frequency may be divided by a factor in the range from 1 to 2 16 . 10.4.2.13 autodiscriminator mode the phase difference sign of two overlapping puls- es (respectively on txinb and txina) generates a one step up/down count, so that the up/down con- trol and the counter clock are both external. the setting of the udc bit in the tcr register has no effect in this configuration. figure 98. parallel mode description prescaler 0 prescaler 1 mft1 intclk/3 note: mft 1 is not available on all devices. refer to counter block diagram and register map. the device mft0 counter 9
190/398 multifunction timer (mft) multifunction timer (contd) 10.4.3 input pin assignment the two external inputs (txina and txinb) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by programming the two relevant bits (a0, a1 and b0, b1) for each input in the external input control register (t_icr). the 16 different functional modes of the two exter- nal inputs can be selected by programming bits in0 - in3 of the t_icr, as illustrated in figure 39 table 39. input pin function some choices relating to the external input pin as- signment are defined in conjunction with the rm0 and rm1 bits in tmr. for input pin assignment codes which use the in- put pins as trigger inputs (except for code 1010, trigger up:trigger down), the following conditions apply: C a trigger signal on the txina input pin performs an u/d counter load if rm0 is reset, or an exter- nal capture if rm0 is set. C a trigger signal on the txinb input pin always performs an external capture on reg1r. the txinb input pin is disabled when the bivalue mode is set. note : for proper operation of the external input pins, the following must be observed: C the minimum external clock/trigger pulse width must not be less than the system clock (intclk) period if the input pin is programmed as rising or falling edge sensitive. C the minimum external clock/trigger pulse width must not be less than the prescaler clock period (intclk/3) if the input pin is programmed as ris- ing and falling edge sensitive (valid also in auto discrimination mode). C the minimum delay between two clock/trigger pulse active edges must be greater than the prescaler clock period (intclk/3), while the minimum delay between two consecutive clock/ trigger pulses must be greater than the system clock (intclk) period. C the minimum gate pulse width must be at least twice the prescaler clock period (intclk/3). C in autodiscrimination mode, the minimum delay between the input pin a pulse edge and the edge of the input pin b pulse, must be at least equal to the system clock (intclk) period. C if a number, n, of external pulses must be count- ed using a compare register in external clock mode, then the compare register must be load- ed with the value [x +/- (n-1)], where x is the starting counter value and the sign is chosen de- pending on whether up or down count mode is selected. i c reg. in3-in0 bits txina input function txinb input function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate 9
191/398 multifunction timer (mft) multifunction timer (contd) 10.4.3.1 txina = i/o - txinb = i/o input pins a and b are not used by the timer. the counter clock is internally generated and the up/ down selection may be made only by software via the udc (software up/down) bit in the tcr regis- ter. 10.4.3.2 txina = i/o - txinb = trigger the signal applied to input pin b acts as a trigger signal on reg1r register. the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (soft- ware up/down) bit in the tcr register. 10.4.3.3 txina = gate - txinb = i/o the signal applied to input pin a acts as a gate sig- nal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). the counter clock is internally generated and the up/down con- trol may be made only by software via the udc (software up/down) bit in the tcr register. 10.4.3.4 txina = gate - txinb = trigger both input pins a and b are connected to the timer, with the resulting effect of combining the actions relating to the previously described configurations. 10.4.3.5 txina = i/o - txinb = ext. clock the signal applied to input pin b is used as the ex- ternal clock for the prescaler. the up/down selec- tion may be made only by software via the udc (software up/down) bit in the tcr register. 10.4.3.6 txina = trigger - txinb = i/o the signal applied to input pin a acts as a trigger for reg0r, initiating the action for which the reg- ister was programmed (i.e. a reload or capture). the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register. (*) the timer is in one shot mode and regor in reload mode 10.4.3.7 txina = gate - txinb = ext. clock the signal applied to input pin b, gated by the sig- nal applied to input pin a, acts as external clock for the prescaler. the up/down control may be made only by software action through the udc bit in the tcr register. 10.4.3.8 txina = trigger - txinb = trigger the signal applied to input pin a (or b) acts as trig- ger signal for reg0r (or reg1r), initiating the action for which the register has been pro- grammed. the counter clock is internally generat- ed and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register. 9
192/398 multifunction timer (mft) multifunction timer (contd) 10.4.3.9 txina = clock up - txinb = clock down the edge received on input pin a (or b) performs a one step up (or down) count, so that the counter clock and the up/down control are external. setting the udc bit in the tcr register has no effect in this configuration, and input pin b has priority on input pin a. 10.4.3.10 txina = up/down - txinb = ext clock an high (or low) level applied to input pin a sets the counter in the up (or down) count mode, while the signal applied to input pin b is used as clock for the prescaler. setting the udc bit in the tcr reg- ister has no effect in this configuration. 10.4.3.11 txina = trigger up - txinb = trigger down up/down control is performed through both input pins a and b. a edge on input pin a sets the up count mode, while a edge on input pin b (which has priority on input pin a) sets the down count mode. the counter clock is internally generated, and setting the udc bit in the tcr register has no effect in this configuration. 10.4.3.12 txina = up/down - txinb = i/o an high (or low) level of the signal applied on in- put pin a sets the counter in the up (or down) count mode. the counter clock is internally generated. setting the udc bit in the tcr register has no ef- fect in this configuration. 9
193/398 multifunction timer (mft) multifunction timer (contd) 10.4.3.13 autodiscrimination mode the phase between two pulses (respectively on in- put pin b and input pin a) generates a one step up (or down) count, so that the up/down control and the counter clock are both external. thus, if the ris- ing edge of txinb arrives when txina is at a low level, the timer is incremented (no action if the ris- ing edge of txinb arrives when txina is at a high level). if the falling edge of txinb arrives when txina is at a low level, the timer is decremented (no action if the falling edge of txinb arrives when txina is at a high level). setting the udc bit in the tcr register has no ef- fect in this configuration. 10.4.3.14 txina = trigger - txinb = ext. clock the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b is used as the clock for the prescaler. (*) the timer is in one shot mode and reg0r in reload mode 10.4.3.15 txina = ext. clock - txinb = trigger the signal applied to input pin b acts as a trigger, performing a capture on reg1r, while the signal applied to input pin a is used as the clock for the prescaler. 10.4.3.16 txina = trigger - txinb = gate the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b acts as a gate signal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). 9
194/398 multifunction timer (mft) multifunction timer (contd) 10.4.4 output pin assignment two external outputs are available when pro- grammed as alternate function outputs of the i/o pins. two registers output a control register (oacr) and output b control register (obcr) define the driver for the outputs and the actions to be per- formed. each of the two output pins can be driven from any of the three possible sources: C compare register 0 event logic C compare register 1 event logic C overflow/underflow event logic. each of these three sources can cause one of the following four actions on any of the two outputs: C nop C set C reset C toggle furthermore an on chip event signal can be driv- en by two of the three sources: the over/under- flow event and compare 0 event by programming the cev bit of the oacr register and the oev bit of obcr register respectively. this signal can be used internally to synchronise another on-chip pe- ripheral. output waveforms depending on the programming of oacr and ob- cr, the following example waveforms can be gen- erated on txouta and txoutb pins. for a configuration where txouta is driven by the over/underflow (ouf) and the compare 0 event (cm0), and txoutb is driven by the over/under- flow and compare 1 event (cm1): oacr is programmed with txouta preset to 0, ouf sets txouta, cm0 resets txouta and cm1 does not affect the output. obcr is programmed with txoutb preset to 0, ouf sets txoutb, cm1 resets txoutb while cm0 does not affect the output. for a configuration where txouta is driven by the over/underflow, by compare 0 and by compare 1; txoutb is driven by both compare 0 and com- pare 1. oacr is programmed with txouta pre- set to 0. ouf toggles output 0, as do cm0 and cm1. obcr is programmed with txoutb preset to 1. ouf does not affect the output; cm0 resets txoutb and cm1 sets it. oacr = [101100x0] obcr = [111000x0] t0outa t0outb ouf comp1 ouf comp1 ouf comp0 ouf comp0 oacr = [010101x0] obcr = [100011x1] t0outa t0outb comp1 comp1 ouf ouf comp0 comp0 comp0 comp0 comp1 comp1 9
195/398 multifunction timer (mft) multifunction timer (contd) for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by the over/underflow and by compare 1. oacr is programmed with txouta preset to 0. ouf sets txouta while cm0 resets it, and cm1 has no effect. obcr is programmed with tx- outb preset to 1. ouf toggles txoutb, cm1 sets it and cm0 has no effect. for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by compare 0 and 1. oacr is pro- grammed with txouta preset to 0. ouf sets txouta, cm0 resets it and cm1 has no effect. obcr is programmed with txoutb preset to 0. ouf has no effect, cm0 sets txoutb and cm1 toggles it. output waveform samples in biload mode txouta is programmed to monitor the two time intervals, t1 and t2, of the biload mode, while tx- outb is independent of the over/underflow and is driven by the different values of compare 0 and compare 1. oacr is programmed with txouta preset to 0. ouf toggles the output and cm0 and cm1 do not affect txouta. obcr is programmed with txoutb preset to 0. ouf has no effect, while cm1 resets txoutb and cm0 sets it. depending on the cm1/cm0 values, three differ- ent sample waveforms have been drawn based on the above mentioned configuration of obcr. in the last case, with a different programmed value of obcr, only compare 0 drives txoutb, toggling the output. note (*) depending on the cmp1r/cmp0r values oacr = [101100x0] obcr = [000111x0] t0outa t0outb ouf ouf comp0 comp0 comp0 comp0 comp1 comp1 9
196/398 multifunction timer (mft) multifunction timer (contd) 10.4.5 interrupt and dma 10.4.5.1 timer interrupt the timer has 5 different interrupt sources, be- longing to 3 independent groups, which are as- signed to the following interrupt vectors: table 40. timer interrupt structure the three least significant bits of the vector pointer address represent the relative priority assigned to each group, where 000 represents the highest pri- ority level. these relative priorities are fixed by hardware, according to the source which gener- ates the interrupt request. the 5 most significant bits represent the general priority and are pro- grammed by the user in the interrupt vector reg- ister (t_ivr). each source can be masked by a dedicated bit in the interrupt/dma mask register (idmr) of each timer, as well as by a global mask enable bit (id- mr.7) which masks all interrupts. if an interrupt request (cm0 or cp0) is present be- fore the corresponding pending bit is reset, an overrun condition occurs. this condition is flagged in two dedicated overrun bits, relating to the comp0 and capt0 sources, in the timer flag reg- ister (t_flagr). 10.4.5.2 timer dma two independent dma channels, associated with comp0 and capt0 respectively, allow dma trans- fers from register file or memory to the comp0 register, and from the capt0 register to register file or memory). if dma is enabled, the capt0 and comp0 interrupts are generated by the corre- sponding dma end of block event. their priority is set by hardware as follows: C compare 0 destination lower priority C capture 0 source higher priority the two dma request sources are independently maskable by the cp0d and cm0d dma mask bits in the idmr register. the two dma end of block interrupts are inde- pendently enabled by the cp0i and cm0i interrupt mask bits in the idmr register. 10.4.5.3 dma pointers the 6 programmable most significant bits of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr) are com- mon to both channels (comp0 and capt0). the comp0 and capt0 address pointers are mapped as a pair in the register file, as are the comp0 and capt0 dma counter pair. in order to specify either the capt0 or the comp0 pointers, according to the channel being serviced, the timer resets address bit 1 for capt0 and sets it for comp0, when the d0 bit in the dcpr regis- ter is equal to zero (word address in register file). in this case (transfers between peripheral registers and memory), the pointers are split into two groups of adjacent address and counter pairs respectively. for peripheral register to register transfers (select- ed by programming 1 into bit 0 of the dcpr reg- ister), only one pair of pointers is required, and the pointers are mapped into one group of adjacent positions. the dma address pointer register (dapr) is not used in this case, but must be considered re- served. figure 99. pointer mapping for transfers between registers and memory interrupt source vector address comp 0 comp 1 xxxx x110 capt 0 capt 1 xxxx x100 overflow/underflow xxxx x000 register file address pointers comp0 16 bit addr pointer yyyyyy11(l) yyyyyy10(h) capt0 16 bit addr pointer yyyyyy01(l) yyyyyy00(h) dma counters comp0 dma 16 bit counter xxxxxx11(l) xxxxxx10(h) capt0 dma 16 bit counter xxxxxx01(l) xxxxxx00(h) 9
197/398 multifunction timer (mft) multifunction timer (contd) figure 100. pointer mapping for register to register transfers 10.4.5.4 dma transaction priorities each timer dma transaction is a 16-bit operation, therefore two bytes must be transferred sequen- tially, by means of two dma transfers. in order to speed up each word transfer, the second byte transfer is executed by automatically forcing the peripheral priority to the highest level (000), re- gardless of the previously set level. it is then re- stored to its original value after executing the transfer. thus, once a request is being serviced, its hardware priority is kept at the highest level re- gardless of the other timer internal sources, i.e. once a comp0 request is being serviced, it main- tains a higher priority, even if a capt0 request oc- curs between the two byte transfers. 10.4.5.5 dma swap mode after a complete data table transfer, the transac- tion counter is reset and an end of block (eob) condition occurs, the block transfer is completed. the end of block interrupt routine must at this point reload both address and counter pointers of the channel referred to by the end of block inter- rupt source, if the application requires a continu- ous high speed data flow. this procedure causes speed limitations because of the time required for the reload routine. the swap feature overcomes this drawback, al- lowing high speed continuous transfers. bit 2 of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr), tog- gles after every end of block condition, alternately providing odd and even address (d2-d7) for the pair of pointers, thus pointing to an updated pair, after a block has been completely transferred. this allows the user to update or read the first block and to update the pointer values while the second is being transferred. these two toggle bits are soft- ware writable and readable, mapped in dcpr bit 2 for the cm0 channel, and in dapr bit 2 for the cp0 channel (though a dma event on a channel, in swap mode, modifies a field in dapr and dcpr common to both channels, the dapr/ dcpr content used in the transfer is always the bit related to the correct channel). swap mode can be enabled by the swen bit in the idcr register. warning : enabling swap mode affects both channels (cm0 and cp0). register file 8 bit counter xxxxxx11 compare 0 8 bit addr pointer xxxxxx10 8 bit counter xxxxxx01 capture 0 8 bit addr pointer xxxxxx00 9
198/398 multifunction timer (mft) multifunction timer (contd) 10.4.5.6 dma end of block interrupt routine an interrupt request is generated after each block transfer (eob) and its priority is the same as that assigned in the usual interrupt request, for the two channels. as a consequence, they will be serviced only when no dma request occurs, and will be subject to a possible ouf interrupt request, which has higher priority. the following is a typical eob procedure (with swap mode enabled): C test toggle bit and jump. C reload pointers (odd or even depending on tog- gle bit status). C reset eob bit: this bit must be reset only after the old pair of pointers has been restored, so that, if a new eob condition occurs, the next pair of pointers is ready for swapping. C verify the software protection condition (see section 10.4.5.7 ). C read the corresponding overrun bit: this con- firms that no dma request has been lost in the meantime. C reset the corresponding pending bit. C reenable dma with the corresponding dma mask bit (must always be done after resetting the pending bit) C return. warning : the eob bits are read/write only for test purposes. writing a logical 1 by software (when the swen bit is set) will cause a spurious interrupt request. these bits are normally only re- set by software. 10.4.5.7 dma software protection a second eob condition may occur before the first eob routine is completed, this would cause a not yet updated pointer pair to be addressed, with con- sequent overwriting of memory. to prevent these errors, a protection mechanism is provided, such that the attempted setting of the eob bit before it has been reset by software will cause the dma mask on that channel to be reset (dma disabled), thus blocking any further dma operation. as shown above, this mask bit should always be checked in each eob routine, to ensure that all dma transfers are properly served. 10.4.6 register description note: in the register description on the following pages, register and page numbers are given using the example of timer 0. on devices with more than one timer, refer to the device register map for the adresses and page numbers. 9
199/398 multifunction timer (mft) multifunction timer (contd) capture load 0 high register (reg0hr) r240 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 0 low register (reg0lr) r241 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). capture load 1 high register (reg1hr) r242 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 1 low register (reg1lr) r243 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). compare 0 high register (cmp0hr) r244 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 0 low register (cmp0lr) r245 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. compare 1 high register (cmp1hr) r246 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 1 low register (cmp1lr) r247 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 9
200/398 multifunction timer (mft) multifunction timer (contd) timer control register (tcr) r248 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cen : counter enable . this bit is anded with the global counter enable bit (gcen) in the cicr register (r230). the gcen bit is set after the reset cycle. 0: stop the counter and prescaler 1: start the counter and prescaler (without reload). note: even if cen=0, capture and loading will take place on a trigger event. bit 6 = ccp0 : clear on capture . 0: no effect 1: clear the counter and reload the prescaler on a reg0r or reg1r capture event bit 5 = ccmp0 : clear on compare . 0: no effect 1: clear the counter and reload the prescaler on a cmp0r compare event bit 4 = ccl : counter clear . this bit is reset by hardware after being set by software (this bit always returns 0 when read). 0: no effect 1: clear the counter without generating an inter- rupt request bit 3 = udc : up/down software selection . if the direction of the counter is not fixed by hard- ware (txina and/or txinb pins, see par. 10.3) it can be controlled by software using the udc bit. 0: down counting 1: up counting bit 2 = udcs : up/down count status . this bit is read only and indicates the direction of the counter. 0: down counting 1: up counting bit 1 = of0 : ovf/unf state . this bit is read only. 0: no overflow or underflow occurred 1: overflow or underflow occurred during a cap- ture on register 0 bit 0 = cs counter status . this bit is read only and indicates the status of the counter. 0: counter halted 1: counter running 70 cen ccp0 ccmp0 ccl udc udcs of0 cs 9
201/398 multifunction timer (mft) multifunction timer (contd) timer mode register (tmr) r249 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = oe1 : output 1 enable. 0: disable the output 1 (txoutb pin) and force it high. 1: enable the output 1 (txoutb pin) the relevant i/o bit must also be set to alternate function bit 6 = oe0 : output 0 enable. 0: disable the output 0 (txouta pin) and force it high 1: enable the output 0 (txouta pin). the relevant i/o bit must also be set to alternate function bit 5 = bm : bivalu e mode . this bit works together with the rm1 and rm0 bits to select the timer operating mode (see table 41 ). 0: disable bivalue mode 1: enable bivalue mode bit 4 = rm1 : reg1r mode . this bit works together with the bm and rm0 bits to select the timer operating mode. refer to table 41 . note: this bit has no effect when the bivalue mode is enabled (bm=1). bit 3 = rm0 : reg0r mode . this bit works together with the bm and rm1 bits to select the timer operating mode. refer to table 41 . table 41. timer operating modes bit 2 = eck timer clock control . 0: the prescaler clock source is selected depend- ing on the in0 - in3 bits in the t_icr register 1: enter parallel mode (for timer 1 and timer 3 only, no effect for timer 0 and 2). see section 10.4.2.12 . bit 1 = ren : retrigger mode . 0: enable retriggerable mode 1: disable retriggerable mode bit 0 = co : continous/one shot mode . 0: continuous mode (with autoreload on end of count condition) 1: one shot mode 70 oe1 oe0 bm rm1 rm0 eck ren c0 tmr bits timer operating modes bm rm1 rm0 1 x 0 biload mode 1 x 1 bicapture mode 00 0 load from reg0r and monitor on reg1r 01 0 load from reg0r and capture on reg1r 00 1 capture on reg0r and monitor on reg1r 0 1 1 capture on reg0r and reg1r 9
202/398 multifunction timer (mft) multifunction timer (contd) external input control register (t_icr) r250 - read/write register page: 10 reset value: 0000 0000 (00h) bits 7:4 = in[3:0] : input pin function. these bits are set and cleared by software. bits 3:2 = a[0:1] : txina pin event . these bits are set and cleared by software. bits 1:0 = b[0:1]: txinb pin event . these bits are set and cleared by software. prescaler register (prsr) r251 - read/write register page: 10 reset value: 0000 0000 (00h) this register holds the preset value for the 8-bit prescaler. the prsr content may be modified at any time, but it will be loaded into the prescaler at the following prescaler underflow, or as a conse- quence of a counter reload (either by software or upon external request). following a reset condition, the prescaler is au- tomatically loaded with 00h, so that the prescaler divides by 1 and the maximum counter clock is generated (crystal oscillator clock frequency divid- ed by 6 when moder.5 = div2 bit is set). the binary value programmed in the prsr regis- ter is equal to the divider value minus one. for ex- ample, loading prsr with 24 causes the prescal- er to divide by 25. 70 in3 in2 in1 in0 a0 a1 b0 b1 in[3:0] bits txina pin function txinb input pin function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate a0 a1 txina pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges b0 b1 txinb pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges 70 p7 p6 p5 p4 p3 p2 p1 p0 9
203/398 multifunction timer (mft) multifunction timer (contd) output a control register (oacr) r252 - read/write register page: 10 reset value: 0000 0000 bits 7:6 = c0e[0:1] : comp0 action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when a successful compare of the cmp0r register occurs. refer to table 42 for the list of actions that can be configured. bits 5:4 = c1e[0:1]: comp1 action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when a successful compare of the cmp1r register occurs. refer to table 42 for the list of actions that can be configured. bits 3:2 = oue[0:1] : ovf/unf action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when an overflow or underflow of the u/d counter occurs. refer to table 42 for the list of actions that can be configured. table 42. output a action bits notes: C xx stands for c0, c1 or ou. C whenever more than one event occurs simulta- neously, action bit 0 will be the result of anding action bit 0 of all simultaneous events and action bit 1 will be the result of anding action bit 1 of all simultaneous events. bit 1 = cev : on-chip event on cmp0r . this bit is set and cleared by software. 0: no action 1: a successful compare on cmp0r activates the on-chip event signal (a single pulse is generat- ed) bit 0 = op : txouta preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txouta pin. reading this bit returns the current state of the txouta pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 cev 0p xxe0 xxe1 action on txouta pin when an xx event occurs 0 0 set 0 1 toggle 1 0 reset 1 1 nop 9
204/398 multifunction timer (mft) multifunction timer (contd) output b control register (obcr) r253 - read/write register page: 10 reset value: 0000 0000 (00h) bits 7:6 = c0e[0:1] : comp0 action bits . these bits are set and cleared by software. they configure the type of action to be performed on the txoutb output pin when successful compare of the cmp0r register occurs. refer to table 43 for the list of actions that can be configured. bits 5:4 = c0e[0:1]: comp1 action bits . these bits are set and cleared by software. they configure the type of action to be performed on the txoutb output pin when a successful compare of the cmp1r register occurs. refer to table 43 for the list of actions that can be configured. bits 3:2 = oue[0:1] : ovf/unf action bits . these bits are set and cleared by software.they configure the type of action to be performed on the txoutb output pin when an overflow or under- flow on the u/d counter occurs. refer to table 43 for the list of actions that can be configured. table 43. output b action bits notes: C xx stands for c0, c1 or ou. C whenever more than one event occurs simulta- neously, action bit 0 will be the result of anding action bit 0 of all simultaneous events and action bit 1 will be the result of anding action bit 1 of all simultaneous events. bit 1 = oev : on-chip event on ovf/unf . this bit is set and cleared by software. 0: no action 1: an underflow/overflow activates the on-chip event signal (a single pulse is generated) bit 0 = op : txoutb preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txoutb pin. reading this bit returns the current state of the txoutb pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 oev 0p xxe0 xxe1 action on the txoutb pin when an xx event occurs 0 0 set 0 1 toggle 1 0 reset 1 1 nop 9
205/398 multifunction timer (mft) multifunction timer (contd) flag register (t_flagr) r254 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cp0 : capture 0 flag. this bit is set by hardware after a capture on reg0r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp0 bit must be cleared by software. setting by software acts as a software load/cap- ture to/from the reg0r register. 0: no capture 0 event 1: capture 0 event occurred bit 6 = cp1 : capture 1 flag . this bit is set by hardware after a capture on reg1r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp1 bit must be cleared by software. setting by software acts as a capture event on the reg1r register, except when in bicapture mode. 0: no capture 1 event 1: capture 1 event occurred bit 5 = cm0 : compare 0 flag . this bit is set by hardware after a successful com- pare on the cmp0r register. an interrupt is gener- ated if the gtien and cm0i bits in the idmr reg- ister are set. the cm0 bit is cleared by software. 0: no compare 0 event 1: compare 0 event occurred bit 4 = cm1 : compare 1 flag. this bit is set after a successful compare on cmp1r register. an interrupt is generated if the gtien and cm1i bits in the idmr register are set. the cm1 bit is cleared by software. 0: no compare 1 event 1: compare 1 event occurred bit 3 = ouf : overflow/underflow . this bit is set by hardware after a counter over/ underflow condition. an interrupt is generated if gtien and oui=1 in the idmr register. the ouf bit is cleared by software. 0: no counter overflow/underflow 1: counter overflow/underflow bit 2 = ocp0 : overrun on capture 0. this bit is set by hardware when more than one int/dma requests occur before the cp0 flag is cleared by software or whenever a capture is sim- ulated by setting the cp0 flag by software. the ocp0 flag is cleared by software. 0: no capture 0 overrun 1: capture 0 overrun bit 1 = ocm0 : overrun on compare 0. this bit is set by hardware when more than one int/dma requests occur before the cm0 flag is cleared by software.the ocm0 flag is cleared by software. 0: no compare 0 overrun 1: compare 0 overrun bit 0 = a0 : capture interrupt function . this bit is set and cleared by software. 0: configure the capture interrupt as an or func- tion of reg0r/reg1r captures 1: configure the capture interrupt as an and func- tion of reg0r/reg1r captures note: when a0 is set, both cp0i and cp1i in the idmr register must be set to enable both capture interrupts. 70 cp0 cp1 cm0 cm1 ouf ocp0 ocm0 a0 9
206/398 multifunction timer (mft) multifunction timer (contd) interrupt/dma mask register (idmr) r255 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = gtien : global timer interrupt enable . this bit is set and cleared by software. 0: disable all timer interrupts 1: enable all timer timer interrupts from enabled sources bit 6 = cp0d : capture 0 dma mask. this bit is set by software to enable a capt0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable capture on reg0r dma 1: enable capture on reg0r dma bit 5 = cp0i : capture 0 interrupt mask . 0: disable capture on reg0r interrupt 1: enable capture on reg0r interrupt (or capt0 dma end of block interrupt if cp0d=1) bit 4 = cp1i : capture 1 interrupt mask . this bit is set and cleared by software. 0: disable capture on reg1r interrupt 1: enable capture on reg1r interrupt bit 3 = cm0d : compare 0 dma mask. this bit is set by software to enable a comp0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable compare on cmp0r dma 1: enable compare on cmp0r dma bit 2 = cm0i : compare 0 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp0r interrupt 1: enable compare on cmp0r interrupt (or comp0 dma end of block interrupt if cm0d=1) bit 1 = cm1i : compare 1 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp1r interrupt 1: enable compare on cmp1r interrupt bit 0 = oui : overflow/underflow interrupt mask . this bit is set and cleared by software. 0: disable overflow/underflow interrupt 1: enable overflow/underflow interrupt dma counter pointer register (dcpr) r240 - read/write register page: 9 reset value: undefined bits 7:2 = dcp[7:2] : msbs of dma counter regis- ter address. these are the most significant bits of the dma counter register address programmable by soft- ware. the dcp2 bit may also be toggled by hard- ware if the timer dma section for the compare 0 channel is configured in swap mode. bit 1 = dma-srce : dma source selection. this bit is set and cleared by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on cmp0r reg- ister bit 0 = reg/mem : dma area selection . this bit is set and cleared by software. it selects the source and destination of the dma area 0: dma from/to memory 1: dma from/to register file 70 gtien cp0d cp0i cp1i cm0d cm0i cm1i oui 70 dcp7 dcp6 dcp5 dcp4 dcp3 dcp2 dma srce reg/ mem 9
207/398 multifunction timer (mft) multifunction timer (contd) dma address pointer register (dapr) r241 - read/write register page: 9 reset value: undefined bits 7:2 = dap[7:2] : msb of dma address regis- ter location. these are the most significant bits of the dma ad- dress register location programmable by software. the dap2 bit may also be toggled by hardware if the timer dma section for the compare 0 channel is configured in swap mode. note: during a dma transfer with the register file, the dapr is not used; however, in swap mode, dap2 is used to point to the correct table. bit 1 = dma-srce : dma source selection. this bit is fixed by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on the cmp0r register bit 0 = prg/dat: dma memory selection . this bit is set and cleared by software. it is only meaningful if dcpr.reg/mem=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). interrupt vector register (t_ivr) r242 - read/write register page: 9 reset value: xxxx xxx0 this register is used as a vector, pointing to the 16-bit interrupt vectors in memory which contain the starting addresses of the three interrupt sub- routines managed by each timer. only one interrupt vector register is available for each timer, and it is able to manage three interrupt groups, because the 3 least significant bits are fixed by hardware depending on the group which generated the interrupt request. in order to determine which request generated the interrupt within a group, the t_flagr register can be used to check the relevant interrupt source. bits 7:3 = v[4:0]: msb of the vector address. these bits are user programmable and contain the five most significant bits of the timer interrupt vec- tor addresses in memory. in any case, an 8-bit ad- dress can be used to indicate the timer interrupt vector locations, because they are within the first 256 memory locations (see interrupt and dma chapters). bits 2:1 = w[1:0]: vector address bits. these bits are equivalent to bit 1 and bit 2 of the timer interrupt vector addresses in memory. they are fixed by hardware, depending on the group of sources which generated the interrupt request as follows:. bit 0 = this bit is forced by hardware to 0. 70 dap7 dap6 dap5 dap4 dap3 dap2 dma srce prg /dat reg/mem prg/dat dma source/destination 0 0 1 1 0 1 0 1 isr register used to address memory dmasr register used to address memory register file register file 70 v4 v3 v2 v1 v0 w1 w0 0 w1 w0 interrupt source 0 0 1 1 0 1 0 1 overflow/underflow even interrupt not available capture event interrupt compare event interrupt 9
208/398 multifunction timer (mft) multifunction timer (contd) interrupt/dma control register (idcr) r243 - read/write register page: 9 reset value: 1100 0111 (c7h) bit 7 = cpe : capture 0 eob . this bit is set by hardware when the end of block condition is reached during a capture 0 dma op- eration with the swap mode enabled. when swap mode is disabled (swen bit = 0), the cpe bit is forced to 1 by hardware. 0: no end of block condition 1: capture 0 end of block bit 6 = cme : compare 0 eob . this bit is set by hardware when the end of block condition is reached during a compare 0 dma op- eration with the swap mode enabled. when the swap mode is disabled (swen bit = 0), the cme bit is forced to 1 by hardware. 0: no end of block condition 1: compare 0 end of block bit 5 = dcts : dma capture transfer source . this bit is set and cleared by software. it selects the source of the dma operation related to the channel associated with the capture 0. note: the i/o port source is available only on spe- cific devices. 0: reg0r register 1: i/o port. bit 4 = dctd : dma compare transfer destination . this bit is set and cleared by software. it selects the destination of the dma operation related to the channel associated with compare 0. note: the i/o port destination is available only on specific devices. 0: cmp0r register 1: i/o port bit 3 = swen : swap function enable . this bit is set and cleared by software. 0: disable swap mode 1: enable swap mode for both dma channels. bits 2:0 = pl[2:0]: interrupt/dma priority level . with these three bits it is possible to select the in- terrupt and dma priority level of each timer, as one of eight levels (see interrupt/dma chapter). i/o connection register (iocr) r248 - read/write register page: 9 reset value: 1111 1100 (fch) bits 7:2 = not used. bit 1 = sc1 : select connection odd. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 1 and timer 3 are connected on-chip or not. 0: t1outa / t1ina and t3outa/ t3ina uncon- nected 1: t1outa connected internally to t1ina and t3outa connected internally to t3ina bit 0 = sc0 : select connection even. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 0 and timer 2 are connected on-chip or not. 0: t0outa / t0ina and t2outa/ t2ina uncon- nected 1: t0outa connected internally to t0ina and t2outa connected internally to t2ina note: timer 1 and 2 are available only on some devices. refer to the device block diagram and register map. 70 cpe cme dcts dctd swen pl2 pl1 pl0 70 sc1 sc0 9
209/398 multiprotocol serial communications interface (sci-m) 10.5 multiprotocol serial communications interface (sci-m) 10.5.1 introduction the multiprotocol serial communications inter- face (sci-m) offers full-duplex serial data ex- change with a wide range of external equipment. the sci-m offers four operating modes: asynchro- nous, asynchronous with synchronous clock, seri- al expansion and synchronous. 10.5.2 main features n full duplex synchronous and asynchronous operation. n transmit, receive, line status, and device address interrupt generation. n integral baud rate generator capable of dividing the input clock by any value from 2 to 2 16 -1 (16 bit word) and generating the internal 16x data sampling clock for asynchronous operation or the 1x clock for synchronous operation. n fully programmable serial interface: C 5, 6, 7, or 8 bit word length. C even, odd, or no parity generation and detec- tion. C 0, 1, 1.5, 2, 2.5, 3 stop bit generation. C complete status reporting capabilities. C line break generation and detection. n programmable address indication bit (wake-up bit) and user invisible compare logic to support multiple microcomputer networking. optional character search function. n internal diagnostic capabilities: C local loopback for communications link fault isolation. C auto-echo for communications link fault isola- tion. n separate interrupt/dma channels for transmit and receive. n in addition, a synchronous mode supports: C high speed communication C possibility of hardware synchronization (rts/ dcd signals). C programmable polarity and stand-by level for data sin/sout. C programmable active edge and stand-by level for clocks clkout/rxcl. C programmable active levels of rts/dcd sig- nals. C full loop-back and auto-echo modes for da- ta, clocks and controls. figure 101. sci-m block diagram transmit buffer register register shift transmit register shift receiver function alternate register compare address register buffer receiver dma controller clock and baud rate generator st9 core bus sout txclk/clkout rxclk sin va00169a frame control and status dma controller rts dcd sds 9
210/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.3 functional description the sci-m has four operating modes: C asynchronous mode C asynchronous mode with synchronous clock C serial expansion mode C synchronous mode asynchronous mode, asynchronous mode with synchronous clock and serial expansion mode output data with the same serial frame format. the differences lie in the data sampling clock rates (1x, 16x) and in the protocol used. figure 102. sci -m functional schematic note: some pins may not be available on some devices. refer to the device pinout description. divider by 16 1 0 1 0 divider by 16 cd cd the control signals marked with (*) are active only in synchronous mode (smen=1) polarity polarity txclk / clkout rx shift register tx buffer register tx shift register rtsen (*) enveloper aen (*) outsb (*) stand by polarity sout aen rx buffer register polarity polarity stand by polarity baud rate generator rxclk ocksb (*) lben (*) intclk xbrg aen (*) oclk xtclk dcden (*) dcd rts sin inpl (*) lben outpl (*) inpen (*) ockpl (*) xrx oclk vr02054 9
211/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.4 sci-m operating modes 10.5.4.1 asynchronous mode in this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received data), each data bit is sampled 16 times per clock period. the baud rate clock should be set to the 16 mode and the frequency of the input clock (from an ex- ternal source or from the internal baud-rate gener- ator output) is set to suit. 10.5.4.2 asynchronous mode with synchronous clock in this mode, data and clock are synchronous, each data bit is sampled once per clock period. for transmit operation, a general purpose i/o port pin can be programmed to output the clkout signal from the baud rate generator. if the sci is provided with an external transmission clock source, there will be a skew equivalent to two intclk periods between clock and data. data will be transmitted on the falling edge of the transmit clock. received data will be latched into the sci on the rising edge of the receive clock. figure 103. sampling times in asynchronous format 012345 7 8 9 101112131415 sdin rcvck rxd rxclk vr001409 legend: sin: rcvck: rxd: rxclk: serial data input line internal x16 receiver clock internal serial data input line internal receiver shift register sampling clock 9
212/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.4.3 serial expansion mode this mode is used to communicate with an exter- nal synchronous peripheral. the transmitter only provides the clock waveform during the period that data is being transmitted on the clkout pin (the data envelope). data is latched on the rising edge of this clock. whenever the sci is to receive data in serial port expansion mode, the clock must be supplied ex- ternally, and be synchronous with the transmitted data. the sci latches the incoming data on the ris- ing edge of the received clock, which is input on the rxclk pin. 10.5.4.4 synchronous mode this mode is used to access an external synchro- nous peripheral, dummy start/stop bits are not in- cluded in the data frame. polarity, stand-by level and active edges of i/o signals are fully and sepa- rately programmable for both inputs and outputs. it's necessary to set the smen bit of the synchro- nous input control register (sicr) to enable this mode and all the related extra features (otherwise disabled). the transmitter will provide the clock waveform only during the period when the data is being transmitted via the clkout pin, which can be en- abled by setting both the xtclk and oclk bits of the clock configuration register. whenever the sci is to receive data in synchronous mode, the clock waveform must be supplied externally via the rxclk pin and be synchronous with the data. for correct receiver operation, the xrx bit of the clock configuration register must be set. two external signals, request-to-send and data- carrier-detect (rts/dcd), can be enabled to syn- chronise the data exchange between two serial units. the rts output becomes active just before the first active edge of clkout and indicates to the target device that the mcu is about to send a synchronous frame; it returns to its stand-by state following the last active edge of clkout (msb transmitted). the dcd input can be considered as a gate that filters rxclk and informs the mcu that a trans- mitting device is transmitting a data frame. polarity of rts/dcd is individually programmable, as for clocks and data. the data word is programmable from 5 to 8 bits, as for the other modes; parity, address/9th, stop bits and break cannot be inserted into the transmitted frame. programming of the related bits of the sci control registers is irrelevant in synchronous mode: all the corresponding interrupt requests must, in any case, be masked in order to avoid in- correct operation during data reception. 9
213/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) figure 104. sci -m operating modes note: in all operating modes, the least significant bit is transmitted/received first. asynchronous mode asynchronous mode with synchronous clock serial expansion mode synchronous mode i/o clock start bit data parity stop bit 16 16 16 va00271 i/o clock start bit data parity stop bit va00272 i/o clock data va0273a start bit (dummy) stop bit (dummy) stand-by clock data vr02051 stand-by stand-by stand-by rts/dcd stand-by stand-by 9
214/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.5 serial frame format characters sent or received by the sci can have some or all of the features in the following format, depending on the operating mode: start : the start bit indicates the beginning of a data frame in asynchronous modes. the start condition is detected as a high to low transition. a dummy start bit is generated in serial expan- sion mode. the start bit is not generated in synchronous mode. data : the data word length is programmable from 5 to 8 bits, for both synchronous and asyn- chronous modes. lsb are transmitted first. parity : the parity bit (not available in serial ex- pansion mode and synchronous mode) is option- al, and can be used with any word length. it is used for error checking and is set so as to make the total number of high bits in data plus parity odd or even, depending on the number of 1s in the data field. address/9th : the address/9th bit is optional and may be added to any word format. it is used in both serial expansion and asynchronous modes to indicate that the data is an address (bit set). the address/9th bit is useful when several mi- crocontrollers are exchanging data on the same serial bus. individual microcontrollers can stay idle on the serial bus, waiting for a transmitted ad- dress. when a microcontroller recognizes its own address, it can begin data reception, likewise, on the transmit side, the microcontroller can transmit another address to begin communication with a different microcontroller. the address/9th bit can be used as an addi- tional data bit or to mark control words (9th bit). stop : indicates the end of a data frame in asyn- chronous modes. a dummy stop bit is generated in serial expansion mode. the stop bit can be programmed to be 1, 1.5, 2, 2.5 or 3 bits long, de- pending on the mode. it returns the sci to the qui- escent marking state (i.e., a constant high-state condition) which lasts until a new start bit indicates an incoming word. the stop bit is not generated in synchronous mode. figure 105. sci character formats (1) lsb first (2) not available in synchronous mode (3) not available in serial expansion mode and synchronous mode start (2) data (1) parity (3) address (2) stop (2) # bits 1 5, 6, 7, 8 0, 1 0, 1 1, 1.5, 2, 2.5, 1, 2, 3 16x 1x states none odd even on off 9
215/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.5.1 data transfer data to be transmitted by the sci is first loaded by the program into the transmitter buffer register. the sci will transfer the data into the transmitter shift register when the shift register becomes available (empty). the transmitter shift register converts the parallel data into serial format for transmission via the sci alternate function out- put, serial data out. on completion of the transfer, the transmitter buffer register interrupt pending bit will be updated. if the selected word length is less than 8 bits, the unused most significant bits do not need to be defined. incoming serial data from the serial data input pin is converted into parallel format by the receiver shift register. at the end of the input data frame, the valid data portion of the received word is trans- ferred from the receiver shift register into the re- ceiver buffer register. all receiver interrupt con- ditions are updated at the time of transfer. if the selected character format is less than 8 bits, the unused most significant bits will be set. the frame control and status block creates and checks the character configuration (data length and number of stop bits), as well as the source of the transmitter/receiver clock. the internal baud rate generator contains a pro- grammable divide by n counter which can be used to generate the clocks for the transmitter and/or receiver. the baud rate generator can use intclk or the receiver clock input via rxclk. the address bit/d9 is optional and may be added to any word in asynchronous and serial expan- sion modes. it is commonly used in network or ma- chine control applications. when enabled (ab set), an address or ninth data bit can be added to a transmitted word by setting the set address bit (sa). this is then appended to the next word en- tered into the (empty) transmitter buffer register and then cleared by hardware. on character input, a set address bit can indicate that the data pre- ceding the bit is an address which may be com- pared in hardware with the value in the address compare register (acr) to generate an address match interrupt when equal. the address bit and address comparison regis- ter can also be combined to generate four different types of address interrupt to suit different proto- cols, based on the status of the address mode en- able bit (amen) and the address mode bit (am) in the chcr register. the character match address interrupt mode may be used as a powerful character search mode, generating an interrupt on reception of a predeter- mined character e.g. carriage return or end of block codes (character match interrupt). this is the only address interrupt mode available in syn- chronous mode. the line break condition is fully supported for both transmission and reception. line break is sent by setting the sb bit (idpr). this causes the trans- mitter output to be held low (after all buffered data has been transmitted) for a minimum of one com- plete word length and until the sb bit is reset. break cannot be inserted into the transmitted frame for the synchronous mode. testing of the communications channel may be performed using the built-in facilities of the sci pe- ripheral. auto-echo mode and loop-back mode may be used individually or together. in asynchro- nous, asynchronous with synchronous clock and serial expansion modes they are available only on sin/sout pins through the programming of aen/ lben bits in ccr. in synchronous mode (smen set) the above configurations are available on sin/ sout, rxclk/clkout and dcd/rts pins by programming the aen/lben bits and independ- ently of the programmed polarity. in the synchro- nous mode case, when aen is set, the transmitter outputs (data, clock and control) are disconnected from the i/o pins, which are driven directly by the receiver input pins (auto-echo mode: sout=sin, clkout=rxclk and rts=dcd, even if they act on the internal receiver with the programmed po- larity/edge). when lben is set, the receiver inputs (data, clock and controls) are disconnected and the transmitter outputs are looped-back into the re- ceiver section (loop-back mode: sin=sout, rx- clk=clkout, dcd=rts. the output pins are locked to their programmed stand-by level and the status of the inpl, xckpl, dcdpl, outpl, ockpl and rtspl bits in the sicr register are ir- relevant). refer to figure 106 , figure 107 , and figure 108 for these different configurations. table 44. address interrupt modes (1) not available in synchronous mode if 9th data bit is set (1) if character match if character match and 9th data bit is set (1) if character match immediately follows break (1) 9
216/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) figure 106. auto echo configuration figure 107. loop back configuration figure 108. auto echo and loop-back configuration all modes except synchronous synchronous mode (smen=1) receiver sin sout vr000210 transmitter receiver sin sout vr00210a transmitter dcd rts rxclk clkout all modes except synchronous synchronous mode (smen=1) receiver sin sout vr000211 transmitter logical 1 receiver sin sout vr00211a transmitter dcd rts rxclk clkout stand-by value stand-by value stand-by value clock data all modes except synchronous synchronous mode (smen=1) receiver sin sout vr000212 transmitter receiver sin sout vr00212a transmitter dcd rts rxclk clkout clock data 9
217/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.6 clocks and serial transmission rates the communication bit rate of the sci transmitter and receiver sections can be provided from the in- ternal baud rate generator or from external sources. the bit rate clock is divided by 16 in asynchronous mode (cd in ccr reset), or undi- vided in the 3 other modes (cd set). with intclk running at 24mhz and no external clock provided, a maximum bit rate of 3mbaud and 750kbaud is available in undivided and divide by-16-mode respectively. with intclk running at 24mhz and an external clock provided through the rxclk/txclk lines, a maximum bit rate of 3mbaud and 375kbaud is available in undivided and divided by 16 mode re- spectively (see figure 110 ). external clock sources. the external clock in- put pin txclk may be programmed by the xtclk and oclk bits in the ccr register as: the transmit clock input, baud rate generator output (allowing an external divider circuit to provide the receive clock for split rate transmit and receive), or as clkout output in synchronous and serial ex- pansion modes. the rxclk receive clock input is enabled by the xrx bit, this input should be set in accordance with the setting of the cd bit. baud rate generator. the internal baud rate generator consists of a 16-bit programmable di- vide by n counter which can be used to generate the transmitter and/or receiver clocks. the mini- mum baud rate divisor is 2 and the maximum divi- sor is 2 16 -1. after initialising the baud rate genera- tor, the divisor value is immediately loaded into the counter. this prevents potentially long random counts on the initial load. the baud rate generator frequency is equal to the input clock frequency divided by the divisor value. warning: programming the baud rate divider to 0 or 1 will stop the divider. the output of the baud rate generator has a pre- cise 50% duty cycle. the baud rate generator can use intclk for the input clock source. in this case, intclk (and therefore the mcu xtal) should be chosen to provide a suitable frequency for division by the baud rate generator to give the required transmit and receive bit rates. suitable intclk frequencies and the respective divider values for standard baud rates are shown in table 45 . 10.5.7 sci -m initialization procedure writing to either of the two baud rate generator registers immediately disables and resets the sci baud rate generator, as well as the transmitter and receiver circuitry. after writing to the second baud rate generator register, the transmitter and receiver circuits are enabled. the baud rate generator will load the new value and start counting. to initialize the sci, the user should first initialize the most significant byte of the baud rate gener- ator register; this will reset all sci circuitry. the user should then initialize all other sci registers (sicr/socr included) for the desired operating mode and then, to enable the sci, he should ini- tialize the least significant byte baud rate gener- ator register. 'on-the-fly' modifications of the control registers' content during transmitter/receiver operations, al- though possible, can corrupt data and produce un- desirable spikes on the i/o lines (data, clock and control). furthermore, modifying the control regis- ters' content without reinitialising the sci circuitry (during stand-by cycles, waiting to transmit or re- ceive data) must be kept carefully under control by software to avoid spurious data being transmitted or received. note : for synchronous receive operation, the data and receive clock must not exhibit significant skew between clock and data. the received data and clock are internally synchronized to intclk. figure 109. sci-m baud rate generator initialization sequence select sci working mode least significant byte initialization most significant byte initialization 9
218/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) table 45. sci-m baud rate generator divider values example 1 table 46. sci-m baud rate generator divider values example 2 intclk: 19660.800 khz baud rate clock factor desired freq (khz) divisor actual baud rate actual freq (khz) deviation dec hex 50.00 16 x 0.80000 24576 6000 50.00 0.80000 0.0000% 75.00 16 x 1.20000 16384 4000 75.00 1.20000 0.0000% 110.00 16 x 1.76000 11170 2ba2 110.01 1.76014 -0.00081% 300.00 16 x 4.80000 4096 1000 300.00 4.80000 0.0000% 600.00 16 x 9.60000 2048 800 600.00 9.60000 0.0000% 1200.00 16 x 19.20000 1024 400 1200.00 19.20000 0.0000% 2400.00 16 x 38.40000 512 200 2400.00 38.40000 0.0000% 4800.00 16 x 76.80000 256 100 4800.00 76.80000 0.0000% 9600.00 16 x 153.60000 128 80 9600.00 153.60000 0.0000% 19200.00 16 x 307.20000 64 40 19200.00 307.20000 0.0000% 38400.00 16 x 614.40000 32 20 38400.00 614.40000 0.0000% 76800.00 16 x 1228.80000 16 10 76800.00 1228.80000 0.0000% intclk: 24576 khz baud rate clock factor desired freq (khz) divisor actual baud rate actual freq (khz) deviation dec hex 50.00 16 x 0.80000 30720 7800 50.00 0.80000 0.0000% 75.00 16 x 1.20000 20480 5000 75.00 1.20000 0.0000% 110.00 16 x 1.76000 13963 383b 110.01 1.76014 -0.00046% 300.00 16 x 4.80000 5120 1400 300.00 4.80000 0.0000% 600.00 16 x 9.60000 2560 a00 600.00 9.60000 0.0000% 1200.00 16 x 19.20000 1280 500 1200.00 19.20000 0.0000% 2400.00 16 x 38.40000 640 280 2400.00 38.40000 0.0000% 4800.00 16 x 76.80000 320 140 4800.00 76.80000 0.0000% 9600.00 16 x 153.60000 160 a0 9600.00 153.60000 0.0000% 19200.00 16 x 307.20000 80 50 19200.00 307.20000 0.0000% 38400.00 16 x 614.40000 40 28 38400.00 614.40000 0.0000% 76800.00 16 x 1228.80000 20 14 76800.00 1228.80000 0.0000% 9
219/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.8 input signals sin: serial data input . this pin is the serial data input to the sci receiver shift register. txclk: external transmitter clock input . this pin is the external input clock driving the sci trans- mitter. the txclk frequency must be greater than or equal to 16 times the transmitter data rate (de- pending whether the x16 or the x1 clock have been selected). a 50% duty cycle is required for this input and must have a period of at least twice intclk. the use of the txclk pin is optional. rxclk: external receiver clock input. this in- put is the clock to the sci receiver when using an external clock source connected to the baud rate generator. intclk is normally the clock source. a 50% duty cycle is required for this input and must have a period of at least twice intclk. use of rx- clk is optional. dcd: data carrier detect. this input is enabled only in synchronous mode; it works as a gate for the rxclk clock and informs the mcu that an emitting device is transmitting a synchronous frame. the active level can be programmed as 1 or 0 and must be provided at least one intclk pe- riod before the first active edge of the input clock. 10.5.9 output signals sout: serial data output. this alternate func- tion output signal is the serial data output for the sci transmitter in all operating modes. clkout: clock output . the alternate function of this pin outputs either the data clock from the transmitter in serial expansion or synchronous modes, or the clock output from the baud rate generator. in serial expansion mode it will clock only the data portion of the frame and its stand-by state is high: data is valid on the rising edge of the clock. even in synchronous mode clkout will only clock the data portion of the frame, but the stand-by level and active edge polarity are pro- grammable by the user. when synchronous mode is disabled (smen in sicr is reset), the state of the xtclk and oclk bits in ccr determine the source of clkout; '11' enables the serial expansion mode. when the synchronous mode is enabled (smen in sicr is set), the state of the xtclk and oclk bits in ccr determine the source of clkout; '00' disables it for plm applications. rts: request to send. this output alternate function is only enabled in synchronous mode; it becomes active when the least significant bit of the data frame is sent to the serial output pin (sout) and indicates to the target device that the mcu is about to send a synchronous frame; it re- turns to its stand-by value just after the last active edge of clkout (msb transmitted). the active level can be programmed high or low. sds: synchronous data strobe. this output al- ternate function is only enabled in synchronous mode; it becomes active high when the least sig- nificant bit is sent to the serial output pins (sout) and indicates to the target device that the mcu is about to send the first bit for each synchro- nous frame. it is active high on the first bit and it is low for all the rest of the frame. the active level can not be programmed. figure 110. receiver and transmitter clock frequencies note: the internal receiver and transmitter clocks are the ones applied to the tx and rx shift regis- ters (see figure 101 ). min max conditions receiver clock frequency external rxclk 0 intclk/8 1x mode 0 intclk/4 16x mode internal receiver clock 0 intclk/8 1x mode 0 intclk/2 16x mode transmitter clock frequency external txclk 0 intclk/8 1x mode 0 intclk/4 16x mode internal transmitter clock 0 intclk/8 1x mode 0 intclk/2 16x mode 9
220/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.10 interrupts and dma 10.5.10.1 interrupts the sci can generate interrupts as a result of sev- eral conditions. receiver interrupts include data pending, receive errors (overrun, framing and par- ity), as well as address or break pending. trans- mitter interrupts are software selectable for either transmit buffer register empty (bsn set) or for transmit shift register empty (bsn reset) condi- tions. typical usage of the interrupts generated by the sci peripheral are illustrated in figure 111 . the sci peripheral is able to generate interrupt re- quests as a result of a number of events, several of which share the same interrupt vector. it is therefore necessary to poll s_isr, the interrupt status register, in order to determine the active trigger. these bits should be reset by the program- mer during the interrupt service routine. the four major levels of interrupt are encoded in hardware to provide two bits of the interrupt vector register, allowing the position of the block of point- er vectors to be resolved to an 8 byte block size. the sci interrupts have an internal priority struc- ture in order to resolve simultaneous events. refer also to section 10.5.4 sci-m operating modes for more details relating to synchronous mode. table 47. sci interrupt internal priority receive dma request highest priority transmit dma request receive interrupt transmit interrupt lowest priority 9
221/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) table 48. sci-m interrupt vectors figure 111. sci-m interrupts: example of typical usage interrupt source vector address transmitter buffer or shift register empty transmit dma end of block xxx x110 received data pending receive dma end of block xxxx x100 break detector address word match xxxx x010 receiver error xxxx x000 interrupt break match address data address after break condition address word marked by d9=1 address interrupt interrupt d9=1 d9 acting as data control with separate interrupt character search mode interrupt va00270 break break interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt interrupt interrupt data address data data data data no match address break data no match address match data data data match data char match data data data data address data data d9=1 data data data data 9
222/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.10.2 dma two dma channels are associated with the sci, for transmit and for receive. these follow the reg- ister scheme as described in the dma chapter. dma reception to perform a dma transfer in reception mode: 1. initialize the dma counter (rdcpr) and dma address (rdapr) registers 2. enable dma by setting the rxd bit in the idpr register. 3. dma transfer is started when data is received by the sci. dma transmission to perform a dma transfer in transmission mode: 1. initialize the dma counter (tdcpr) and dma address (tdapr) registers. 2. enable dma by setting the txd bit in the idpr register. 3. dma transfer is started by writing a byte in the transmitter buffer register (txbr). if this byte is the first data byte to be transmitted, the dma counter and address registers must be initialized to begin dma transmission at the sec- ond byte. alternatively, dma transfer can be start- ed by writing a dummy byte in the txbr register. dma interrupts when dma is active, the received data pending and the transmitter shift register empty interrupt sources are replaced by the dma end of block re- ceive and transmit interrupt sources. note: to handle dma transfer correctly in trans- mission, the bsn bit in the imr register must be cleared. this selects the transmitter shift register empty event as the dma interrupt source. the transfer of the last byte of a dma data block will be followed by a dma end of block transmit or receive interrupt, setting the txeob or rxeob bit. a typical transmission end of block interrupt rou- tine will perform the following actions: 1. restore the dma counter register (tdcpr). 2. restore the dma address register (tdapr). 3. clear the transmitter shift register empty bit txsem in the s_isr register to avoid spurious interrupts. 4. clear the transmitter end of block (txeob) pending bit in the imr register. 5. set the txd bit in the idpr register to enable dma. 6. load the transmitter buffer register (txbr) with the next byte to transmit. the above procedure handles the case where a further dma transfer is to be performed. error interrupt handling if an error interrupt occurs while dma is enabled in reception mode, dma transfer is stopped. to resume dma transfer, the error interrupt han- dling routine must clear the corresponding error flag. in the case of an overrun error, the routine must also read the rxbr register. character search mode with dma in character search mode with dma, when a character match occurs, this character is not trans- ferred. dma continues with the next received char- acter. to avoid an overrun error occurring, the character match interrupt service routine must read the rxbr register. 9
223/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) 10.5.11 register description the sci-m registers are located in the following pages in the st9: sci-m number 0: page 24 (18h) sci-m number 1: page 25 (19h) (when present) the sci is controlled by the following registers: address register r240 (f0h) receiver dma transaction counter pointer register r241 (f1h) receiver dma source address pointer register r242 (f2h) transmitter dma transaction counter pointer register r243 (f3h) transmitter dma destination address pointer register r244 (f4h) interrupt vector register r245 (f5h) address compare register r246 (f6h) interrupt mask register r247 (f7h) interrupt status register r248 (f8h) receive buffer register same address as transmitter buffer register (read only) r248 (f8h) transmitter buffer register same address as receive buffer register (write only) r249 (f9h) interrupt/dma priority register r250 (fah) character configuration register r251 (fbh) clock configuration register r252 (fch) baud rate generator high register r253 (fdh) baud rate generator low register r254 (feh) synchronous input control register r255 (ffh) synchronous output control register 9
224/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) receiver dma counter pointer (rdcpr) r240 - read/write reset value: undefined bit 7:1 = rc[7:1] : receiver dma counter pointer. these bits contain the address of the receiver dma transaction counter in the register file. bit 0 = rr/m : receiver register file/memory se- lector . 0: select memory space as destination. 1: select the register file as destination. receiver dma address pointer (rdapr) r241 - read/write reset value: undefined bit 7:1 = ra[7:1] : receiver dma address pointer. these bits contain the address of the pointer (in the register file) of the receiver dma data source. bit 0 = rps : receiver dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (rr/m = 0 in the rdcpr register). 0: select isr register for receiver dma transfers address extension. 1: select dmasr register for receiver dma trans- fers address extension. transmitter dma counter pointer (tdcpr) r242 - read/write reset value: undefined bit 7:1 = tc[7:1] : transmitter dma counter point- er . these bits contain the address of the transmitter dma transaction counter in the register file. bit 0 = tr/m : transmitter register file/memory selector . 0: select memory space as source. 1: select the register file as source. transmitter dma address pointer (tdapr) r243 - read/write reset value: undefined bit 7:1 = ta[7:1] : transmitter dma address point- er. these bits contain the address of the pointer (in the register file) of the transmitter dma data source. bit 0 = tps : transmitter dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (tr/m = 0 in the tdcpr register). 0: select isr register for transmitter dma transfers address extension. 1: select dmasr register for transmitter dma transfers address extension. 70 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rr/m 70 ra7 ra6 ra5 ra4 ra3 ra2 ra1 rps 70 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tr/m 70 ta7 ta6 ta5 ta4 ta3 ta2 ta1 tps 9
225/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) interrupt vector register (s_ivr) r244 - read/write reset value: undefined bit 7:3 = v[7:3] : sci interrupt vector base ad- dress. user programmable interrupt vector bits for trans- mitter and receiver. bit 2:1 = ev[2:1] : encoded interrupt source. both bits ev2 and ev1 are read only and set by hardware according to the interrupt source. bit 0 = d0 : this bit is forced by hardware to 0. address/data compare register (acr) r245 - read/write reset value: undefined bit 7:0 = ac[7:0] : address/compare character . with either 9th bit address mode, address after break mode, or character search, the received ad- dress will be compared to the value stored in this register. when a valid address matches this regis- ter content, the receiver address pending bit (rxap in the s_isr register) is set. after the rxap bit is set in an addressed mode, all received data words will be transferred to the receiver buff- er register. 70 v7 v6 v5 v4 v3 ev2 ev1 0 ev2 ev1 interrupt source 0 0 receiver error (overrun, framing, parity) 0 1 break detect or address match 10 received data pending/receiver dma end of block 11 transmitter buffer or shift register empty transmitter dma end of block 70 ac7ac6ac5ac4ac3ac2ac1ac0 9
226/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) interrupt mask register (imr) r246 - read/write reset value: 0xx00000 bit 7 = bsn : buffer or shift register empty inter- rupt . this bit selects the source of the transmitter regis- ter empty interrupt. 0: select a shift register empty as source of a transmitter register empty interrupt. 1: select a buffer register empty as source of a transmitter register empty interrupt. bit 6 = rxeob : received end of block. this bit is set by hardware only and must be reset by software. rxeob is set after a receiver dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a received block of data. bit 5 = txeob : transmitter end of block. this bit is set by hardware only and must be reset by software. txeob is set after a transmitter dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a transmitted block of data. bit 4 = rxe : receiver error mask. 0: disable receiver error interrupts (oe, pe, and fe pending bits in the s_isr register). 1: enable receiver error interrupts. bit 3 = rxa : receiver address mask . 0: disable receiver address interrupt (rxap pending bit in the s_isr register). 1: enable receiver address interrupt. bit 2 = rxb : receiver break mask . 0: disable receiver break interrupt (rxbp pend- ing bit in the s_isr register). 1: enable receiver break interrupt. bit 1 = rxdi : receiver data interrupt mask . 0: disable receiver data pending and receiver end of block interrupts (rxdp and rxeob pending bits in the s_isr register). 1: enable receiver data pending and receiver end of block interrupts. note: rxdi has no effect on dma transfers. bit 0 = txdi : transmitter data interrupt mask . 0: disable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts (txbem, txsem, and txeob bits in the s_isr register). 1: enable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts. note: txdi has no effect on dma transfers. 70 bsn rxeob txeob rxe rxa rxb rxdi txdi 9
227/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) interrupt status register (s_isr) r247 - read/write reset value: undefined bit 7 = oe : overrun error pending . this bit is set by hardware if the data in the receiv- er buffer register was not read by the cpu before the next character was transferred into the receiv- er buffer register (the previous data is lost). 0: no overrun error. 1: overrun error occurred. bit 6 = fe : framing error pending bit . this bit is set by hardware if the received data word did not have a valid stop bit. 0: no framing error. 1: framing error occurred. note: in the case where a framing error occurs when the sci is programmed in address mode and is monitoring an address, the interrupt is as- serted and the corrupted data element is trans- ferred to the receiver buffer register. bit 5 = pe : parity error pending . this bit is set by hardware if the received word did not have the correct even or odd parity bit. 0: no parity error. 1: parity error occurred. bit 4 = rxap : receiver address pending . rxap is set by hardware after an interrupt ac- knowledged in the address mode. 0: no interrupt in address mode. 1: interrupt in address mode occurred. note: the source of this interrupt is given by the couple of bits (amen, am) as detailed in the idpr register description. bit 3 = rxbp : receiver break pending bit . this bit is set by hardware if the received data in- put is held low for the full word transmission time (start bit, data bits, parity bit, stop bit). 0: no break received. 1: break event occurred. bit 2 = rxdp : receiver data pending bit. this bit is set by hardware when data is loaded into the receiver buffer register. 0: no data received. 1: data received in receiver buffer register. bit 1 = txbem : transmitter buffer register emp- ty . this bit is set by hardware if the buffer register is empty. 0: no buffer register empty event. 1: buffer register empty. bit 0 = txsem : transmitter shift register empty . this bit is set by hardware if the shift register has completed the transmission of the available data. 0: no shift register empty event. 1: shift register empty. note: the interrupt status register bits can be re- set but cannot be set by the user. the interrupt source must be cleared by resetting the related bit when executing the interrupt service routine (natu- rally the other pending bits should not be reset). 70 oe fe pe rxap rxbp rxdp txbem txsem 9
228/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) receiver buffer register (rxbr) r248 - read only reset value: undefined bit 7:0 = rd[7:0] : received data. this register stores the data portion of the re- ceived word. the data will be transferred from the receiver shift register into the receiver buffer register at the end of the word. all receiver inter- rupt conditions will be updated at the time of trans- fer. if the selected character format is less than 8 bits, unused most significant bits will forced to 1. note: rxbr and txbr are two physically differ- ent registers located at the same address. transmitter buffer register (txbr) r248 - write only reset value: undefined bit 7:0 = td[7:0] : transmit data . the st9 core will load the data for transmission into this register. the sci will transfer the data from the buffer into the shift register when availa- ble. at the transfer, the transmitter buffer register interrupt is updated. if the selected word format is less than 8 bits, the unused most significant bits are not significant. note: txbr and rxbr are two physically differ- ent registers located at the same address. 70 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 70 td7 td6 td5 td4 td3 td2 td1 td0 9
229/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) interrupt/dma priority register (idpr) r249 - read/write reset value: undefined bit 7 = amen : address mode enable. this bit, together with the am bit (in the chcr reg- ister), decodes the desired addressing/9th data bit/character match operation. in address mode the sci monitors the input serial data until its address is detected note: upon reception of address, the rxap bit (in the interrupt status register) is set and an inter- rupt cycle can begin. the address character will not be transferred into the receiver buffer regis- ter but all data following the matched sci address and preceding the next address word will be trans- ferred to the receiver buffer register and the proper interrupts updated. if the address does not match, all data following this unmatched address will not be transferred to the receiver buffer reg- ister. in any of the cases the rxap bit must be reset by software before the next word is transferred into the buffer register. when amen is reset and am is set, a useful char- acter search function is performed. this allows the sci to generate an interrupt whenever a specific character is encountered (e.g. carriage return). bit 6 = sb : set break . 0: stop the break transmission after minimum break length. 1: transmit a break following the transmission of all data in the transmitter shift register and the buffer register. note: the break will be a low level on the transmit- ter data output for at least one complete word for- mat. if software does not reset sb before the min- imum break length has finished, the break condi- tion will continue until software resets sb. the sci terminates the break condition with a high level on the transmitter data output for one transmission clock period. bit 5 = sa : set address . if an address/9th data bit mode is selected, sa val- ue will be loaded for transmission into the shift register. this bit is cleared by hardware after its load. 0: indicate it is not an address word. 1: indicate an address word. note: proper procedure would be, when the transmitter buffer register is empty, to load the value of sa and then load the data into the trans- mitter buffer register. bit 4 = rxd : receiver dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a receiver end of block interrupt can occur. 0: disable receiver dma request (the rxdp bit in the s_isr register can request an interrupt). 1: enable receiver dma request (the rxdp bit in the s_isr register can request a dma transfer). bit 3 = txd : transmitter dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a transmitter end of block interrupt can occur. 0: disable transmitter dma request (txbem or txsem bits in s_isr can request an interrupt). 1: enable transmitter dma request (txbem or txsem bits in s_isr can request a dma trans- fer). bit 2:0 = prl[2:0] : sci interrupt/dma priority bits . the priority for the sci is encoded with (prl2,prl1,prl0). priority level 0 is the highest, while level 7 represents no priority. when the user has defined a priority level for the sci, priorities within the sci are hardware defined. these sci internal priorities are: 70 amen sb sa rxd txd prl2 prl1 prl0 amen am 0 0 address interrupt if 9th data bit = 1 0 1 address interrupt if character match 10 address interrupt if character match and 9th data bit =1 11 address interrupt if character match with word immediately following break receiver dma request highest priority transmitter dma request receiver interrupt transmitter interrupt lowest priority 9
230/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) character configuration register (chcr) r250 - read/write reset value: undefined bit 7 = am : address mode . this bit, together with the amen bit (in the idpr register), decodes the desired addressing/9th data bit/character match operation. please refer to the table in the idpr register description. bit 6 = ep : even parity . 0: select odd parity (when parity is enabled). 1: select even parity (when parity is enabled). bit 5 = pen : parity enable . 0: no parity bit. 1: parity bit generated (transmit data) or checked (received data). note: if the address/9th bit is enabled, the parity bit will precede the address/9th bit (the 9th bit is never included in the parity calculation). bit 4 = ab : address/9th bit . 0: no address/9th bit. 1: address/9th bit included in the character format between the parity bit and the first stop bit. this bit can be used to address the sci or as a ninth data bit. bit 3:2 = sb[1:0] : number of stop bits .. bit 1:0 = wl[1:0] : number of data bits 70 am ep pen ab sb1 sb0 wl1 wl0 sb1 sb0 number of stop bits in 16x mode in 1x mode 00 1 1 0 1 1.5 2 10 2 2 1 1 2.5 3 wl1 wl0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits 9
231/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) clock configuration register (ccr) r251 - read/write reset value: 0000 0000 (00h) bit 7 = xtclk this bit, together with the oclk bit, selects the source for the transmitter clock. the following ta- ble shows the coding of xtclk and oclk. bit 6 = oclk this bit, together with the xtclk bit, selects the source for the transmitter clock. the following ta- ble shows the coding of xtclk and oclk. bit 5 = xrx : external receiver clock source . 0: external receiver clock source not used. 1: select the external receiver clock source. note: the external receiver clock frequency must be 16 times the data rate, or equal to the data rate, depending on the status of the cd bit. bit 4 = xbrg : baud rate generator clock source . 0: select intclk for the baud rate generator. 1: select the external receiver clock for the baud rate generator. bit 3 = cd : clock divisor . the status of cd will determine the sci configura- tion (synchronous/asynchronous). 0: select 16x clock mode for both receiver and transmitter. 1: select 1x clock mode for both receiver and transmitter. note: in 1x clock mode, the transmitter will trans- mit data at one data bit per clock period. in 16x mode each data bit period will be 16 clock periods long. bit 2 = aen : auto echo enable . 0: no auto echo mode. 1: put the sci in auto echo mode. note: auto echo mode has the following effect: the sci transmitter is disconnected from the data- out pin sout, which is driven directly by the re- ceiver data-in pin, sin. the receiver remains con- nected to sin and is operational, unless loopback mode is also selected. bit 1 = lben : loopback enable . 0: no loopback mode. 1: put the sci in loopback mode. note: in this mode, the transmitter output is set to a high level, the receiver input is disconnected, and the output of the transmitter shift register is looped back into the receiver shift register input. all interrupt sources (transmitter and receiver) are operational. bit 0 = stpen : stick parity enable . 0: the transmitter and the receiver will follow the parity of even parity bit ep in the chcr register. 1: the transmitter and the receiver will use the op- posite parity type selected by the even parity bit ep in the chcr register. 70 xtclk oclk xrx xbrg cd aen lben stpen xtclk oclk pin function 0 0 pin is used as a general i/o 0 1 pin = txclk (used as an input) 10 pin = clkout (outputs the baud rate generator clock) 11 pin = clkout (outputs the serial expansion and synchronous mode clock) ep spen parity (transmitter & receiver) 0 (odd) 0 odd 1 (even) 0 even 0 (odd) 1 even 1 (even) 1 odd 9
232/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) baud rate generator high register (brghr) r252 - read/write reset value: undefined baud rate generator low register (brglr) r253 - read/write reset value: undefined bit 15:0 = baud rate generator msb and lsb. the baud rate generator is a programmable di- vide by n counter which can be used to generate the clocks for the transmitter and/or receiver. this counter divides the clock input by the value in the baud rate generator register. the minimum baud rate divisor is 2 and the maximum divisor is 2 16 -1. after initialization of the baud rate genera- tor, the divisor value is immediately loaded into the counter. this prevents potentially long random counts on the initial load. if set to 0 or 1, the baud rate generator is stopped. synchronous input control (sicr) r254 - read/write reset value: 0000 0011 (03h) bit 7 = smen : synchronous mode enable . 0: disable all features relating to synchronous mode (the contents of sicr and socr are ig- nored). 1: select synchronous mode with its programmed i/o configuration. bit 6 = inpl : sin input polarity . 0: polarity not inverted. 1: polarity inverted. note: inpl only affects received data. in auto- echo mode sout = sin even if inpl is set. in loop-back mode the state of the inpl bit is irrele- vant. bit 5 = xckpl : receiver clock polarity . 0: rxclk is active on the rising edge. 1: rxclk is active on the falling edge. note: xckpl only affects the receiver clock. in auto-echo mode clkout = rxclk independ- ently of the xckpl status. in loop-back the state of the xckpl bit is irrelevant. bit 4 = dcden : dcd input enable . 0: disable hardware synchronization. 1: enable hardware synchronization. note: when dcden is set, rxclk drives the re- ceiver section only during the active level of the dcd input (dcd works as a gate on rxclk, in- forming the mcu that a transmitting device is sending a synchronous frame to it). bit 3 = dcdpl : dcd input polarity . 0: the dcd input is active when low. 1: the dcd input is active when high. note: dcdpl only affects the gating activity of the receiver clock. in auto-echo mode rts = dcd in- dependently of dcdpl. in loop-back mode, the state of dcdpl is irrelevant. bit 2 = inpen : all input disable . 0: enable sin/rxclk/dcd inputs. 1: disable sin/rxclk/dcd inputs. bit 1:0 = don't care 15 8 bg15 bg14 bg13 bg12 bg11 bg10 bg9 bg8 70 bg7 bg6 bg5 bg4 bg3 bg2 bg1 bg0 70 smen inpl xckpl dcden dcdpl inpen x x 9
233/398 multiprotocol serial communications interface (sci-m) multiprotocol serial communications interface (contd) synchronous output control (socr) r255 - read/write reset value: 0000 0001 (01h) bit 7 = outpl : sout output polarity. 0: polarity not inverted. 1: polarity inverted. note: outpl only affects the data sent by the transmitter section. in auto-echo mode sout = sin even if outpl=1. in loop-back mode, the state of outpl is irrelevant. bit 6 = outsb : sout output stand-by level . 0: sout stand-by level is high. 1: sout stand-by level is low. bit 5 = ockpl : transmitter clock polarity. 0: clkout is active on the rising edge. 1: clkout is active on the falling edge. note: ockpl only affects the transmitter clock. in auto-echo mode clkout = rxclk independ- ently of the state of ockpl. in loop-back mode the state of ockpl is irrelevant. bit 4 = ocksb : transmitter clock stand-by lev- el. 0: the clkout stand-by level is high. 1: the clkout stand-by level is low. bit 3 = rtsen : rts and sds output enable . 0: disable the rts and sds hardware synchroni- sation. 1: enable the rts and sds hardware synchroni- sation. notes: C when rtsen is set, the rts output becomes active just before the first active edge of clk- out and indicates to target device that the mcu is about to send a synchronous frame; it returns to its stand-by value just after the last active edge of clkout (msb transmitted). C when rtsen is set, the sds output becomes active high and indicates to the target device that the mcu is about to send the first bit of a syn- chronous frame on the serial output pin (sout); it returns to low level as soon as the second bit is sent on the serial output pin (sout). in this way a positive pulse is generated each time that the first bit of a synchronous frame is present on the serial output pin (sout). bit 2 = rtspl : rts output polarity. 0: the rts output is active when low. 1: the rts output is active when high. note: rtspl only affects the rts activity on the output pin. in auto-echo mode rts = dcd inde- pendently from the rtspl value. in loop-back mode rtspl value is 'don't care'. bit 1 = outdis : disable all outputs. this feature is available on specific devices only (see device pin-out description). when outdis=1, all output pins (if configured in alternate function mode) will be put in high im- pedance for networking. 0: sout/clkout/enabled 1: sout/clkout/rts put in high impedance bit 0 = don't care 70 outp l outs b ockp l ocks b rtse n rts pl out dis x 9
234/398 asynchronous serial communications interface (sci-a) 10.6 asynchronous serial communications interface (sci-a) 10.6.1 introduction the asynchronous serial communications inter- face (sci-a) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci-a offers a very wide range of baud rates using two baud rate generator sys- tems. 10.6.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 700k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: C overrun error C noise error C frame error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected n parity control: C transmits parity bit C checks parity of received data byte n reduced power consumption mode n lin master: 13-bit lin synch break generation capability 10.6.3 general description the interface is externally connected to another device by two pins (see figure 113 ): C tdo: transmit data output. when the trans- mitter is disabled, the output pin is in high im- pedance. when the transmitter is enabled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data in- put. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is com- plete. this interface uses two types of baud rate genera- tors: C a conventional type for commonly-used baud rates, C an extended type with a prescaler offering a very wide range of baud rates even with non- standard oscillator frequencies. 9
235/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) figure 112. sci-a block diagram wake up unit receiver control scisr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 extended prescaler block diagram line - scicr3 - -- - - - (cf. figure 114 ) 9
236/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.4 functional description the block diagram of the serial control interface, is shown in figure 112 . it contains 6 dedicated registers: C two control registers (scicr1 & scicr2) C a status register (scisr) C a baud rate register (scibrr) C an extended prescaler receiver register (scier- pr) C an extended prescaler transmitter register (sci- etpr) refer to the register descriptions in section 10.6.5 for the definitions of each bit. 10.6.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 112 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 113. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame 9
237/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 112 ). procedure C select the m bit to define the word length. C select the desired baud rate using the scibrr and the scietpr registers. C set the te bit to send an idle frame as first trans- mission. C access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set in the scicr2 register and the imi0 bit is set in the simrh register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the imi0 bit is set in the simrh register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. lin transmission the same procedure has to be applied with the fol- lowing differences: C clear the m bit to configure 8-bit word length C set the line bit to enter lin master mode. in this case, setting the sbk bit will send 13 low bits. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 113 ). as long as the sbk bit is set, the sci sends break frames to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, i.e. before writing the next byte in the scidr. 9
238/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 112 ). procedure C select the m bit to define the word length. C select the desired baud rate using the scibrr and the scierpr registers. C set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the imi0 bit is set in the simrh register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an iterrupt if the ilie bit is set and the imi0 bit is set in the simrh register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the imi0 bit is set in the simrh register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the scidr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read oper- ation followed by a scidr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the scidr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. 9
239/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) figure 114. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register 9
240/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all this bits are in the scibrr register. example: if f cpu is 24 mhz and if pr=13 and tr=rr=2, the transmit and receive baud rates are 57700 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 10.6.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 114 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) 10.6.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a 1 as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. sb : start bit stb : stop bit pb : parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*tr) f cpu m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | 9
241/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.4.7 parity definition even parity: the parity bit is calculated to obtain an even number of 1s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of 1s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of 1s if even parity is selected (ps=0) or an odd number of 1s if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pcie is set in the scicr1 register. 9
242/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) 10.6.5 register description status register (scisr) r240 - read only register page: 26 reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the scisr regis- ter followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the scisr regis- ter followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. 70 tdre tc rdrf idle or nf fe pe 9
243/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error control register 1 (scicr1) r243 - read/write register page: 26 reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on receive data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled note: the itei0 bit in the sitrh register (see in- terrupts chapter) must be set to enable the sci-a interrupt as the sci-a interrupt is a rising edge event. 70 r8 t8 scid m wake pce ps pie 9
244/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) control register 2 (scicr2) r244 - read/write register page: 26 reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is in high impedance 1: transmitter is enabled note: during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the scisr register 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted notes: C if the sbk bit is set to 1 and then to 0, the transmitter will send a break word at the end of the current word. C the itei0 bit in the sitrh register (see inter- rupts chapter) must be set to enable the sci-a interrupt as the sci-a interrupt is a rising edge event. control register 3 (scicr3) r245????????? - read/write register page: 26 reset value: 0000 0000 (00h) bit 7 = reserved bit 6 = line lin mode enable. this bit is set and cleared by software. 0: lin master mode disabled 1: lin master mode enabled the lin master mode enables the capability to send lin synch breaks (13 low bits) using the sbk bit in the scicr2 register. in transmission, the lin synch break low phase duration is shown as below: bits 5:0 = reserved 70 tie tcie rie ilie te re rwu sbk 70 -line----- - line m number of low bits sent during a lin synch break 00 10 01 11 10 13 11 14 9
245/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) data register (scidr) r241 - read/write register page: 26 reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 112 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 112 ). baud rate register (scibrr) r242 - read/write register page: 26 reset value: 00xx xxxx (xxh) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the (tr*etpr) dividing factor. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the (rr*erpr) dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 9
246/398 asynchronous serial communications interface (sci-a) asynchronous serial communications interface (contd) extended receive prescaler division register (scierpr) r245 - read/write register page: 26 reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bits 7:1 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 114 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (scietpr) r246 - read/write register page: 26 reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bits 7:1 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 114 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. 70 erpr7 erpr6 erpr5 erpr4 erpr3 erpr2 erpr1 erpr0 70 etpr7 etpr6 etpr5 etpr4 etpr3 etpr2 etpr1 etpr0 9
247/398 serial peripheral interface (spi) 10.7 serial peripheral interface (spi) 10.7.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 10.7.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n maximum slave mode frequency = intclk/2. n programmable prescalers for a wide range of baud rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 10.7.3 general description the spi is connected to external devices through 4 alternate function pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin to use any of these alternate functions (input or output), the corresponding i/o port must be pro- grammed as alternate function output. a basic example of interconnections between a single master and a single slave is illustrated on figure 115 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave. when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. various data/clock timing relationships may be chosen (see figure 118 ) but master and slave must be programmed with the same timing mode. figure 115. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit 9
248/398 serial peripheral interface (spi) serial peripheral interface (contd) figure 116. serial peripheral interface block diagram spdr read buffer 8-bit shift register write read internal bus spi spie spoe spis mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state spcr spsr - --- - it request master control prescaler /1 .. /8 prs0 prs1 prs2 sppr st9 peripheral clock (intclk) ext. int 0 1 1/2 0 1 div2 9
249/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4 functional description figure 116 shows the serial peripheral interface (spi) block diagram. this interface contains 4 dedicated registers: C a control register (spcr) C a prescaler register (sppr) C a status register (spsr) C a data register (spdr) refer to the spcr, sppr, spsr and spdr reg- isters in section 10.7.6 for the bit definitions. 10.7.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C define the serial clock baud rate by setting/re- setting the div2 bit of sppr register, by writ- ing a prescaler value in the sppr register and programming the spr0 & spr1 bits in the spcr register. C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 118 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spoe bits must be set (they remain set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the spdr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spis and spie bits are set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the spdr register is read, the spi peripheral returns this buffered val- ue. clearing the spif bit is performed by the following software sequence: 1. an access to the spsr register while the spif bit is set 2. a read of the spdr register. note: while the spif bit is set, all writes to the spdr register are inhibited until the spsr regis- ter is read. 9
250/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the sppr register and spr0 & spr1 bits in the spcr is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 118 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spoe bit to assign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spis and spie bits are set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the spdr register is read, the spi peripheral returns this buffered val- ue. clearing the spif bit is performed by the following software sequence: 1. an access to the spsr register while the spif bit is set. 2. a read of the spdr register. notes: while the spif bit is set, all writes to the spdr register are inhibited until the spsr regis- ter is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 10.7.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the spdr register between each data byte transfer to avoid a write collision (see section 10.7.4.4 ). 9
251/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 118 shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 117 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the second clock transition. this pin must be toggled high and low between each byte transmitted (see figure 117 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its spdr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the spdr without produc- ing a write collision. figure 117. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 9
252/398 serial peripheral interface (spi) serial peripheral interface (contd) figure 118. data clock timing diagram msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the spi timing table in the electrical characteristics section. (from slave) sck sck ( cpol = 1 ) ( cpol = 0 ) sck sck ( cpol = 1 ) ( cpol = 0 ) 9
253/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4.4 write collision error a write collision occurs when the software tries to write to the spdr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device spdr register and output the msbit on to the ex- ternal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the spdr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the spdr register without generating a write collision. in master mode collision in the master device is defined as a write of the spdr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the spsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 119 ). figure 119. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1 st step read spsr read spdr 2 nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1 st step 2 nd step wcol=0 read spsr read spdr note: writing in spdr register instead of reading in it do not re- set wcol bit then then 9
254/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spoe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spsr register while the modf bit is set. 2. a write to the spcr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spoe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the user to set the spoe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 10.7.4.6 overrun condition an overrun condition occurs, when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spdr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. 9
255/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 120 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its spdr reg- ister. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spcr register and the modf bit in the spsr register. figure 120. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu 9
256/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.5 interrupt management the interrupt of the serial peripheral interface is mapped on one of the eight external interrupt channels of the microcontroller (refer to the inter- rupts chapter). each external interrupt channel has: C a trigger control bit in the eitr register (r242 - page 0), C a pending bit in the eipr register (r243 - page0), C a mask bit in the eimr register (r244 - page 0). program the interrupt priority level using the ei- plr register (r245 - page 0). for a description of these registers refer to the interrupts and dma chapters. to use the interrupt feature, perform the following sequence: C set the priority level of the interrupt channel used for the spi (eiprl register) C select the interrupt trigger edge as rising edge (set the corresponding bit in the eitr register) C set the spis bit of the spcr register to select the peripheral interrupt source C set the spie bit of the spcr register to enable the peripheral to perform interrupt requests C in the eipr register, reset the pending bit of the interrupt channel used by the spi interrupt to avoid any spurious interrupt requests being per- formed when the mask bit is set C set the mask bit of the interrupt channel used to enable the mcu to acknowledge the interrupt re- quests of the peripheral. note : in the interrupt routine, reset the related pending bit to avoid the interrupt request that was just acknowledged being proposed again. then, after resetting the pending bit and before the iret instruction, check if the spif and modf interrupt flags in the spsr register) are reset; oth- erwise jump to the beginning of the routine. if, on return from an interrupt routine, the pending bit is reset while one of the interrupt flags is set, no in- terrupt is performed on that channel until the flags are set. a new interrupt request is performed only when a flag is set with the other not set. 10.7.5.1 register map depending on the device, one or two serial pe- ripheral interfaces can be present. the previous table summarizes the position of the registers of the two peripherals in the register map of the mi- crocontroller. address page name spi0 r240 (f0h) 7 dr0 r241 (f1h) 7 cr0 r242 (f2h) 7 sr0 r243 (f3h) 7 pr0 spi1 r248 (f8h) 7 dr1 r249 (f9h) 7 cr1 r250 (fah) 7 sr1 r251 (fbh) 7 pr1 9
257/398 serial peripheral interface (spi) serial peripheral interface (contd) 10.7.6 register description data register (spdr) r240 - read/write register page: 7 reset value: 0000 0000 (00h) the spdr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data register, the buffer is ac- tually being read. warning: a write to the spdr register places data directly into the shift register for transmission. a read to the spdr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 116 ). control register (spcr) r241 - read/write register page: 7 reset value: 0000 0000 (00h) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever either spif or modf are set in the spsr register while the other flag is 0. bit 6 = spoe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.7.4.5 master mode fault ). 0: spi alternate functions disabled (miso, mosi and sck can only work as input) 1: spi alternate functions enabled (miso, mosi and sck can work as input or output depending on the value of mstr) note: to use the miso, mosi and sck alternate functions (input or output), the corresponding i/o port must be programmed as alternate function output. bit 5 = spis interrupt selection. this bit is set and cleared by software. 0: interrupt source is external interrupt 1: interrupt source is spi bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.7.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software. they select one of four baud rates to be used as the se- rial clock when the device is a master. these 2 bits have no effect in slave mode. table 49. serial peripheral baud rate 70 d7 d6 d5 d4 d3 d2 d1 d0 70 spie spoe spis mstr cpol cpha spr1 spr0 intclk clock divide spr1 spr0 200 401 16 1 0 32 1 1 9
258/398 serial peripheral interface (spi) serial peripheral interface (contd) status register (spsr) r242 - read only register page: 7 reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spcr register. it is cleared by a soft- ware sequence (an access to the spsr register followed by a read or write to the spdr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the spdr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the spdr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 119 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 10.7.4.5 master mode fault ). an spi interrupt can be gen- erated if spie=1 in the spcr register. this bit is cleared by a software sequence (an access to the spsr register while modf=1 followed by a write to the spcr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3:0 = unused. prescaler register (sppr) r243 - read/write register page: 7 reset value: 0000 0000 (00h) bits 7:5 = reserved, forced by hardware to 0 . bit 4 = div2 divider enable. this bit is set and cleared by software. 0: divider by 2 enabled. 1: divider by 2 disabled. bit 3 = reserved. forced by hardware to 0. bits 2:0 = prs[2:0] prescaler value. these bits are set and cleared by software. the baud rate generator is driven by intclk/(n1*n2*n3) where n1= prs[2:0]+1, n2 is the value defined by the spr[1:0] bits (refer to ta- ble 49 and table 50 ), n3 = 1 if div2=1 and n3= 2 if div2=0. refer to figure 116 . these bits have no effect in slave mode. table 50. prescaler baud rate 70 spifwcol-modf---- 70 0 0 0 div2 0 prs2 prs1 prs0 prescaler division factor prs2 prs1 prs0 1 (no division) 0 0 0 2001 ... 8111 9
259/398 i2c bus interface 10.8 i 2 c bus interface 10.8.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions with both 7-bit and 10-bit address modes; it controls all i 2 c bus-specific sequencing, protocol, arbitration, timing and supports both standard (100khz) and fast i 2 c modes (400khz). using dma, data can be transferred with minimum use of cpu time. the peripheral uses two external lines to perform the protocols: sda, scl. 10.8.2 main features n parallel-bus/i 2 c protocol converter n multi-master capability n 7-bit/10-bit addressing n standard i 2 c mode/fast i 2 c mode n transmitter/receiver flag n end-of-byte transmission flag n transfer problem detection n interrupt generation on error conditions n interrupt generation on transfer request and on data received i 2 c master features: n start bit detection flag n clock generation n i 2 c bus busy flag n arbitration lost flag n end of byte transmission flag n transmitter/receiver flag n stop/start generation i 2 c slave features: n stop bit detection n i 2 c bus busy flag n detection of misplaced start or stop condition n programmable i 2 c address detection (both 7- bit and 10-bit mode) n general call address programmable n transfer problem detection n end of byte transmission flag n transmitter/receiver flag. interrupt features: n interrupt generation on error condition, on transmission request and on data received n interrupt address vector for each interrupt source n pending bit and mask bit for each interrupt source n programmable interrupt priority respects the other peripherals of the microcontroller n interrupt address vector programmable dma features: n dma both in transmission and in reception with enabling bits n dma from/toward both register file and memory n end of block interrupt sources with the related pending bits n selection between dma suspended and dma not-suspended mode if error condition occurs. 9
260/398 i2c bus interface i 2 c bus interface (contd) figure 121. i 2 c interface block diagram 10.8.3 functional description refer to the i2ccr, i2csr1 and i2csr2 registers in section 10.8.7 . for the bit definitions. the i 2 c interface works as an i/o interface between the st9 microcontroller and the i 2 c bus protocol. in addition to receiving and transmitting data, the interface converts data from serial to parallel format and vice versa using an interrupt or polled handshake. it operates in multimaster/slave i 2 c mode. the se- lection of the operating mode is made by software. the i 2 c interface is connected to the i 2 c bus by a data pin (sda) and a clock pin (scl) which must be configured as open drain when the i 2 c cell is enabled by programming the i/o port bits and the pe bit in the i2ccr register. in this case, the value of the external pull-up resistance used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. the i 2 c interface has sixteen internal registers. six of them are used for initialization: C own address registers i2coar1, i2coar2 C general call address register i2cadr C clock control registers i2cccr, i2ceccr C control register i2ccr the following four registers are used during data transmission/reception: C data register i2cdr C control register i2ccr C status register 1 i2csr1 C status register 2 i2csr2 data register data shift register comparator own address register 2 clock control register status register 1 control register control data clock control logic and interrupt/dma registers general call address status register 2 dma data bus control signals interrupt vr02119a sda scl own address register 1 9
261/398 i2c bus interface i 2 c bus interface (contd) the following seven registers are used to handle the interrupt and the dma features: C interrupt status register i2cisr C interrupt mask register i2cimr C interrupt vector register i2civr C receiver dma address pointer register i2crdap C receiver dma transaction counter register i2crdc C transmitter dma address pointer register i2ctdap C transmitter dma transaction counter register i2ctdc the interface can decode both addresses: C software programmable 7-bit general call address C i 2 c address stored by software in the i2coar1 register in 7-bit address mode or stored in i2coar1 and i2coar2 registers in 10-bit ad- dress mode. after a reset, the interface is disabled. important : 1. to guarantee correct operation, before enabling the peripheral (while i2ccr.pe=0), configure bit7 and bit6 of the i2coar2 register according to the internal clock intclk (for example 11xxxxxxb in the range 14 - 30 mhz). 2. bit7 of the i2ccr register must be cleared. 10.8.3.1 mode selection i n i 2 c mode, the interface can operate in the four following modes: C master transmitter/receiver C slave transmitter/receiver by default, it operates in slave mode. this interface automatically switches from slave to master after a start condition is generated on the bus and from master to slave in case of arbitration loss or stop condition generation. in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, it is able to recognize its own ad- dress (7 or 10-bit), as stored in the i2coar1 and i2coar2 registers and (when the i2ccr.engc bit is set) the general call address (stored in i2cadr register). it never recognizes the start byte (address byte 01h) whatever its own address is. data and addresses are transferred in 8 bits, msb first. the first byte(s) following the start condition contain the address (one byte in 7-bit mode, two bytes in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. acknowledge is enabled and disabled by software. refer to figure 122 . 9
262/398 i2c bus interface i 2 c bus interface (contd) figure 122. i 2 c bus protocol any transfer can be done using either the i 2 c registers directly or via the dma. if the transfer is to be done directly by accessing the i2cdr, the interface waits (by holding the scl line low) for software to write in the data register before transmission of a data byte, or to read the data register after a data byte is received. if the transfer is to be done via dma, the interface sends a request for a dma transfer. then it waits for the dma to complete. the transfer between the interface and the i 2 c bus will begin on the next rising edge of the scl clock. the scl frequency (f scl ) generated in master mode is controlled by a programmable clock divid- er. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast (100- 400khz) i 2 c modes. 10.8.4 i 2 c state machine to enable the interface in i 2 c mode the i2ccr.pe bit must be set twice as the first write only acti- vates the interface (only the pe bit is set); and the bit7 of i2ccr register must be cleared. the i 2 c interface always operates in slave mode (the m/sl bit is cleared) except when it initiates a transmission or a receipt sequencing (master mode). the multimaster function is enabled with an auto- matic switch from master mode to slave mode when the interface loses the arbitration of the i 2 c bus. 10.8.4.1 i 2 c slave mode as soon as a start condition is detected, the address word is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. n header (10-bit mode) or address (both 10-bit and 7-bit modes) not matched : the state machine is reset and waits for another start condition. n header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit of the control register (i2ccr) is set. n address matched : the i2csr1.adsl bit is set and an acknowledge bit is sent to the master if the i2ccr.ack bit is set. an interrupt request occurs if the i2ccr.ite bit is set. then the scl line is held low until the microcontroller reads the i2csr1 register (see figure 123 transfer sequencing ev1). scl sda 12 8 9 msb ack stop start condition condition vr02119b 9
263/398 i2c bus interface i 2 c bus interface (contd) next, depending on the data direction bit (least significant bit of the address byte), and after the generation of an acknowledge, the slave must go in sending or receiving mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after i2csr1 register has been read, the slave receives bytes from the sda line into the shift register and sends them to the i2cdr register. after each byte it generates an acknowledge bit if the i2ccr.ack bit is set. when the acknowledge bit is sent, the i2csr1.btf flag is set and an interrupt is generat- ed if the i2ccr.ite bit is set (see figure 123 transfer sequencing ev2). then the interface waits for a read of the i2csr1 register followed by a read of the i2cdr register, or waits for the dma to complete. slave transmitter following the address reception and after i2csr1 register has been read, the slave sends bytes from the i2cdr register to the sda line via the internal shift register. when the acknowledge bit is received, the i2ccr.btf flag is set and an interrupt is generated if the i2ccr.ite bit is set (see figure 123 transfer sequencing ev3). the slave waits for a read of the i2csr1 register followed by a write in the i2cdr register or waits for the dma to complete, both holding the scl line low (except on ev3-1). error cases C berr : detection of a stop or a start condition during a byte transfer. the i2csr2.berr flag is set and an interrupt is generated if i2ccr.ite bit is set. if it is a stop then the state machine is reset. if it is a start then the state machine is reset and it waits for the new slave address on the bus. C af : detection of a no-acknowledge bit. the i2csr2.af flag is set and an interrupt is generated if the i2ccr.ite bit is set. note : in both cases, scl line is not stretched low; however, the sda line, due to possible ?0? bits transmitted last, can remain low. it is then neces- sary to release both lines by software. other events C adsl : detection of a start condition after an ac- knowledge time-slot. the state machine is reset and starts a new proc- ess. the i2csr1.adsl flag bit is set and an in- terrupt is generated if the i2ccr.ite bit is set. the scl line is stretched low. C stopf : detection of a stop condition after an acknowledge time-slot. the state machine is reset. then the i2csr2.stopf flag is set and an interrupt is generated if the i2ccr.ite bit is set. how to release the sda / scl lines check that the i2csr1.busy bit is reset. set and subsequently clear the i2ccr.stop bit while the i2csr1.btf bit is set; then the sda/scl lines are released immediately after the transfer of the cur- rent byte. this will also reset the state machine; any subse- quent stop bit (ev4) will not be detected. 10.8.4.2 i 2 c master mode to switch from default slave mode to master mode a start condition generation is needed. setting the i2ccr.start bit while the i2csr1.busy bit is cleared causes the interface to generate a start condition. once the start condition is generated, the periph- eral is in master mode (i2csr1.m/sl=1) and i2csr1.sb (start bit) flag is set and an interrupt is generated if the i2ccr.ite bit is set (see figure 123 transfer sequencing ev5 event). the interface waits for a read of the i2csr1 regis- ter followed by a write in the i2cdr register with the slave address, holding the scl line low . 9
264/398 i2c bus interface i 2 c bus interface (contd) then the slave address is sent to the sda line. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the i2csr1.evf and i2csr1.add10 bits to be set by hardware with interrupt generation if the i2ccr.ite bit is set. then the master waits for a read of the i2csr1 register followed by a write in the i2cdr register, holding the scl line low (see figure 123 trans- fer sequencing ev9). then the second address byte is sent by the interface. after each address byte, an acknowledge clock pulse is sent to the scl line if the i2csr1.evf and C i2csr1.add10 bit (if first header) C i2csr2.addtx bit (if address or second head- er) are set, and an interrupt is generated if the i2ccr.ite bit is set. the peripheral waits for a read of the i2csr1 reg- ister followed by a write into the control register (i2ccr) by holding the scl line low (see figure 123 transfer sequencing ev6 event). if there was no acknowledge (i2csr2.af=1), the master must stop or restart the communication (set the i2ccr.start or i2ccr.stop bits). if there was an acknowledge, the state machine enters a sending or receiving process according to the data direction bit (least significant bit of the ad- dress), the i2csr1.btf flag is set and an interrupt is generated if i2ccr.ite bit is set (see transfer sequencing ev7, ev8 events). if the master loses the arbitration of the bus there is no acknowledge, the i2csr2.af flag is set and the master must set the start or stop bit in the control register (i2ccr).the i2csr2.arlo flag is set, the i2csr1.m/sl flag is cleared and the proc- ess is reset. an interrupt is generated if i2ccr.ite is set. master transmitter: the master waits for the microcontroller to write in the data register (i2cdr) or it waits for the dma to complete both holding the scl line low (see transfer sequencing ev8). then the byte is received into the shift register and sent to the sda line. when the acknowledge bit is received, the i2csr1.btf flag is set and an interrupt is generated if the i2ccr.ite bit is set or the dma is requested. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver: the master receives a byte from the sda line into the shift register and sends it to the i2cdr regis- ter. it generates an acknowledge bit if the i2ccr.ack bit is set and an interrupt if the i2ccr.ite bit is set or a dma is requested (see transfer sequencing ev7 event). then it waits for the microcontroller to read the data register (i2cdr) or waits for the dma to complete both holding scl line low . error cases n berr : detection of a stop or a start condition during a byte transfer. the i2csr2.berr flag is set and an interrupt is generated if i2ccr.ite is set. n af : detection of a no acknowledge bit the i2csr2.af flag is set and an interrupt is generated if i2ccr.ite is set. n arlo : arbitration lost the i2csr2.arlo flag is set, the i2csr1.m/sl flag is cleared and the process is reset. an interrupt is generated if the i2ccr.ite bit is set. note : in all cases, to resume communications, set the i2ccr.start or i2ccr.stop bits. events generated by the i 2 c interface n stop condition when the i2ccr.stop bit is set, a stop condition is generated after the transfer of the current byte, the i2csr1.m/sl flag is cleared and the state machine is reset. no interrupt is generated in master mode at the detection of the stop condition. n start condition when the i2ccr.start bit is set, a start condition is generated as soon as the i 2 c bus is free. the i2csr1.sb flag is set and an interrupt is generated if the i2ccr.ite bit is set. 9
265/398 i2c bus interface i 2 c bus interface (contd) figure 123. transfer sequencing 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: legend: s=start, sr = repeated start, p=stop, a=acknowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register or when dma is complete. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register or when dma is complete. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register, btf is cleared by releasing the lines (stop=1, stop=0) or writing dr register (for example dr=ffh). note : if lines are released by stop=1, stop=0 the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7 9
266/398 i2c bus interface ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, addtx=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register or when dma is complete. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register or when dma is complete. ev9 : evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. figure 124. event flags and interrupt generation adsl sb af stopf arlo berr add10 addtx ite ierrm ierrp error interrupt request btf=1 & tra=0 receiving dma ite irxm irxp data received interrupt request end of block or end of block btf=1 & tra=1 ite ready to transmit interrupt request or end of block i2csr1.evf reobp itxm itxp teobp transmitting dma end of block 9
267/398 i2c bus interface i 2 c bus interface (contd) 10.8.5 interrupt features the i 2 cbus interface has three interrupt sources related to error condition, peripheral ready to transmit and data received. the peripheral uses the st9+ interrupt internal protocol without requiring the use of the external interrupt channel. dedicated registers of the pe- ripheral should be loaded with appropriate values to set the interrupt vector (see the description of the i2civr register), the interrupt mask bits (see the description of the i2cimr register) and the in- terrupt priority and pending bits (see the descrip- tion of the i2cisr register). the peripheral also has a global interrupt enable (the i2ccr.ite bit) that must be set to enable the interrupt features. moreover there is a global inter- rupt flag (i2csr1.evf bit) which is set when one of the interrupt events occurs (except the end of block interrupts - see the dma features section). the data received interrupt source occurs after the acknowledge of a received data byte is per- formed. it is generated when the i2csr1.btf flag is set and the i2csr1.tra flag is zero. if the dma feature is enabled in receiver mode, this interrupt is not generated and the same inter- rupt vector is used to send a receiving end of block interrupt (see the dma feature section). the peripheral ready to transmit interrupt source occurs as soon as a data byte can be transmitted by the peripheral. it is generated when the i2csr1.btf and the i2csr1.tra flags are set. if the dma feature is enabled in transmitter mode, this interrupt is not generated and the same inter- rupt vector is used to send a transmitting end of block interrupt (see the dma feature section). the error condition interrupt source occurs when one of the following condition occurs: C address matched in slave mode while i2ccr.ack=1 (i2csr1.adsl and i2csr1.evf flags = 1) C start condition generated (i2csr1.sb and i2csr1.evf flags = 1) C no acknowledge received after byte transmis- sion (i2csr2.af and i2csr1.evf flags = 1) C stop detected in slave mode (i2csr2.stopf and i2csr1.evf flags = 1) C arbitration lost in master mode (i2csr2.arlo and i2csr1.evf flags = 1) C bus error, start or stop condition detected during data transfer (i2csr2.berr and i2csr1.evf flags = 1) C master has sent the header byte (i2csr1.add10 and i2csr1.evf flags = 1) C address byte successfully transmitted in master mode. (i2csr1.evf = 1 and i2csr2.addtx=1) note: depending on the value of i2cisr.dmas- top bit, the pending bit related to the error condi- tion interrupt source is able to suspend or not sus- pend dma transfers. each interrupt source has a dedicated interrupt address pointer vector stored in the i2civr regis- ter. the five more significant bits of the vector ad- dress are programmable by the customer, where- as the three less significant bits are set by hard- ware depending on the interrupt source: C 010: error condition detected C 100: data received C 110: peripheral ready to transmit the priority with respect to the other peripherals is programmable by setting the prl[2:0] bits in the i2cisr register. the lowest interrupt priority is ob- tained by setting all the bits (this priority level is never acknowledged by the cpu and is equivalent to disabling the interrupts of the peripheral); the highest interrupt priority is programmed by reset- ting all the bits. see the interrupt and dma chap- ters for more details. the internal priority of the interrupt sources of the peripheral is fixed by hardware with the following order: error condition (highest priority), data received, peripheral ready to transmit. note: the dma has the highest priority over the interrupts; moreover the transmitting end of block interrupt has the same priority as the pe- ripheral ready to transmit interrupt and the re- ceiving end of block interrupt has the same prior- ity as the data received interrupt. each of these three interrupt sources has a pend- ing bit (ierrp, irxp, itxp) in the i2cisr register that is set by hardware when the corresponding in- terrupt event occurs. an interrupt request is per- formed only if the corresponding mask bit is set (ierrm, irxm, itxm) in the i2cimr register and the peripheral has a proper priority level. the pending bit has to be reset by software. 9
268/398 i2c bus interface i 2 c bus interface (contd) note : until the pending bit is reset (while the cor- responding mask bit is set), the peripheral proc- esses an interrupt request. so, if at the end of an interrupt routine the pending bit is not reset, anoth- er interrupt request is performed. note : before the end of the transmission and re- ception interrupt routines, the i2csr1.btf flag bit should be checked, to acknowledge any interrupt requests that occurred during the interrupt routine and to avoid masking subsequent interrupt re- quests. note: the error event interrupt pending bit (i2cisr.ierrp) is forced high when the error event flags are set (add10, adsl and sb flags of the i2csr1 register; sclf, addtx, af, stopf, arlo and berr flags of the i2csr2 register). note: if the i2cisr.dmastop bit is reset, then the dma has the highest priority with respect to the interrupts; if the bit is set (as after the mcu re- set) and the error event pending bit is set (i2cisr.ierrp), then the dma is suspended until the pending bit is reset by software. in the second case, the error interrupt sources have higher pri- ority, followed by dma, data received and re- ceiving end of block interrupts, peripheral ready to transmit and transmitting end of block. moreover the transmitting end of block interrupt has the same priority as the peripheral ready to transmit interrupt and the receiving end of block interrupt has the same priority as the data received interrupt. 10.8.6 dma features the peripheral can use the st9+ on-chip direct memory access (dma) channels to provide high- speed data transaction between the peripheral and contiguous locations of register file, and memory. the transactions can occur from and to- ward the peripheral. the maximum number of transactions that each dma channel can perform is 222 if the register file is selected or 65536 if memory is selected. the control of the dma fea- tures is performed using registers placed in the pe- ripheral register page (i2cisr, i2cimr, i2crdap, i2crdc, i2ctdap, i2ctdc). each dma transfer consists of three operations: C a load from/to the peripheral data register (i2cdr) to/from a location of register file/mem- ory addressed through the dma address regis- ter (or register pair) C a post-increment of the dma address register (or register pair) C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. depending on the value of the i2cisr.dmastop bit the dma feature can be suspended or not (both in transmission and in reception) until the pending bit related to the error event interrupt request is set. the priority level of the dma features of the i 2 c interface with respect to the other peripherals and the cpu is the same as programmed in the i2cisr register for the interrupt sources. in the in- ternal priority level order of the peripheral, if dd- cisr.dmastop=0, dma has a higher priority with respect to the interrupt sources. otherwise (if i2cisr.dmastop=1), the dma has a priority lower than error event interrupt sources but greater than reception and transmission interrupt sources. refer to the interrupt and dma chapters for details on the priority levels. the dma features are enabled by setting the cor- responding enabling bits (rxdm, txdm) in the i2cimr register. it is possible to select also the di- rection of the dma transactions. once the dma transfer is completed (the transac- tion counter reaches 0 value), an interrupt request to the cpu is generated. this kind of interrupt is called end of block. the peripheral sends two different end of block interrupts depending on the direction of the dma (receiving end of block - transmitting end of block). these interrupt sources have dedicated interrupt pending bits in the i2cimr register (reobp, teobp) and they are mapped on the same interrupt vectors as re- spectively data received and peripheral ready to transmit interrupt sources. the same corre- spondence exists about the internal priority be- tween interrupts. note : the i2ccr.ite bit has no effect on the end of block interrupts. moreover, the i2csr1.evf flag is not set by the end of block interrupts. 9
269/398 i2c bus interface i 2 c bus interface (contd) 10.8.6.1 dma between peripheral and register file if the dma transaction is made between the pe- ripheral and the register file, one register is required to hold the dma address and one to hold the dma transaction counter. these two registers must be located in the regis- ter file: C the dma address register in the even ad- dressed register, C the dma transaction counter in the following register (odd address). they are pointed to by the dma transaction counter pointer register (i2crdc register in re- ceiving, i2ctdc register in transmitting) located in the peripheral register page. in order to select the dma transaction with the register file, the control bit i2crdc.rf/mem in receiving mode or i2ctdc.rf/mem in transmit- ting mode must be set. the transaction counter register must be initial- ized with the number of dma transfers to perform and will be decremented after each transaction. the dma address register must be initialized with the starting address of the dma table in the regis- ter file, and it is increased after each transaction. these two registers must be located between ad- dresses 00h and dfh of the register file. when the dma occurs between peripheral and register file, the i2ctdap register (in transmis- sion) and the i2crdap one (in reception) are not used. 10.8.6.2 dma between peripheral and memory space if the dma transaction is made between the pe- ripheral and memory, a register pair is required to hold the dma address and another register pair to hold the dma transaction counter. these two pairs of registers must be located in the register file. the dma address pair is pointed to by the dma address pointer register (i2crdap register in reception, i2ctdap register in transmission) lo- cated in the peripheral register page; the dma transaction counter pair is pointed to by the dma transaction counter pointer register (i2crdc register in reception, i2ctdc register in transmis- sion) located in the peripheral register page. in order to select the dma transaction with the memory space, the control bit i2crdc.rf/mem in receiving mode or i2ctdc.rf/mem in transmit- ting mode must be reset. the transaction counter registers pair must be in- itialized with the number of dma transfers to per- form and will be decremented after each transac- tion. the dma address register pair must be ini- tialized with the starting address of the dma table in the memory space, and it is increased after each transaction. these two register pairs must be located between addresses 00h and dfh of the register file. 10.8.6.3 dma in master receive to correctly manage the reception of the last byte when the dma in master receive mode is used, the following sequence of operations must be per- formed: 1. the number of data bytes to be received must be set to the effective number of bytes minus one byte. 2. when the receiving end of block condition occurs, the i2ccr.stop bit must be set and the i2ccr.ack bit must be reset. the last byte of the reception sequence can be re- ceived either using interrupts/polling or using dma. if the user wants to receive the last byte us- ing dma, the number of bytes to be received must be set to 1, and the dma in reception must be re- enabled (imr.rxdm bit set) to receive the last byte. moreover the receiving end of block inter- rupt service routine must be designed to recognize and manage the two different end of block situa- tions (after the first sequence of data bytes and af- ter the last data byte). 9
270/398 i2c bus interface i 2 c bus interface (contd) 10.8.7 register description important : 1. to guarantee correct operation, before enabling the peripheral (while i2ccr.pe=0), configure bit7 and bit6 of the i2coar2 register according to the internal clock intclk (for example 11xxxxxxb in the range 14 - 30 mhz). 2. bit7 of the i2ccr register must be cleared. i 2 c control register (i2ccr) r240 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) bit 7:6 = reserved must be cleared bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled (reset value) 1: master/slave capability notes: C when i2ccr.pe=0, all the bits of the i2ccr register and the i2csr1-i2csr2 registers ex- cept the stop bit are reset. all outputs will be re- leased while i2ccr.pe=0 C when i2ccr.pe=1, the corresponding i/o pins are selected by hardware as alternate functions (open drain). C to enable the i 2 c interface, write the i2ccr reg- ister twice with i2ccr.pe=1 as the first write only activates the interface (only i2ccr.pe is set). C when pe=1, the freq[2:0] and en10bit bits in the i2coar2 and i2cadr registers cannot be written. the value of these bits can be changed only when pe=0. bit 4 = engc general call address enable. setting this bit the peripheral works as a slave and the value stored in the i2cadr register is recog- nized as device address. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (i2ccr.pe=0). 0: the address stored in the i2cadr register is ignored (reset value) 1: the general call address stored in the i2cadr register will be acknowledged note: the correct value (usually 00h) must be written in the i2cadr register before enabling the general call feature. bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (i2ccr.pe=0) or when the start condition is sent (with interrupt generation if ite=1). C in master mode: 0: no start generation 1: repeated start generation C in slave mode: 0: no start generation (reset value) 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (i2ccr.pe=0). 0: no acknowledge returned (reset value) 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. it is not cleared when the interface is disabled (i2ccr.pe=0). in slave mode, this bit must be set only when i2csr1.btf=1. C in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. C in slave mode: 0: no stop generation (reset value) 1: release scl and sda lines after the current byte transfer (i2csr1.btf=1). in this mode the stop bit has to be cleared by software. 70 0 0 pe engc start ack stop ite 9
271/398 i2c bus interface i 2 c bus interface (contd) bit 0 = ite interrupt enable. the ite bit enables the generation of interrupts. this bit is set and cleared by software and cleared by hardware when the interface is disabled (i2ccr.pe=0). 0: interrupts disabled (reset value) 1: interrupts enabled after any of the following con- ditions: C byte received or to be transmitted (i2csr1.btf and i2csr1.evf flags = 1) C address matched in slave mode while i2ccr.ack=1 (i2csr1.adsl and i2csr1.evf flags = 1) C start condition generated (i2csr1.sb and i2csr1.evf flags = 1) C no acknowledge received after byte transmis- sion (i2csr2.af and i2csr1.evf flags = 1) C stop detected in slave mode (i2csr2.stopf and i2csr1.evf flags = 1) C arbitration lost in master mode (i2csr2.arlo and i2csr1.evf flags = 1) C bus error, start or stop condition detected during data transfer (i2csr2.berr and i2csr1.evf flags = 1) C master has sent header byte (i2csr1.add10 and i2csr1.evf flags = 1) C address byte successfully transmitted in mas- ter mode. (i2csr1.evf = 1 and i2csr2.addtx = 1) scl is held low when the addtx flag of the i2csr2 register or the add10, sb, btf or adsl flags of i2csr1 register are set (see figure 123 ) or when the dma is not complete. the transfer is suspended in all cases except when the btf bit is set and the dma is enabled. in this case the event routine must suspend the dma transfer if it is required. i 2 c status register 1 (i2csr1) r241 - read only register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) note: some bits of this register are reset by a read operation of the register. care must be taken when using instructions that work on single bit. some of them perform a read of all the bits of the register before modifying or testing the wanted bit. so oth- er bits of the register could be affected by the op- eration. in the same way, the test/compare operations per- form a read operation. moreover, if some interrupt events occur while the register is read, the corresponding flags are set, and correctly read, but if the read operation resets the flags, no interrupt request occurs. bit 7 = evf event flag. this bit is set by hardware as soon as an event ( listed below or described in figure 123 ) occurs. it is cleared by software when all event conditions that set the flag are cleared. it is also cleared by hardware when the interface is disabled (i2ccr.pe=0). 0: no event 1: one of the following events has occurred: C byte received or to be transmitted (i2csr1.btf and i2csr1.evf flags = 1) C address matched in slave mode while i2ccr.ack=1 (i2csr1.adsl and i2csr1.evf flags = 1) C start condition generated (i2csr1.sb and i2csr1.evf flags = 1) C no acknowledge received after byte transmis- sion (i2csr2.af and i2csr1.evf flags = 1) C stop detected in slave mode (i2csr2.stopf and i2csr1.evf flags = 1) C arbitration lost in master mode (i2csr2.arlo and i2csr1.evf flags = 1) C bus error, start or stop condition detected during data transfer (i2csr2.berr and i2csr1.evf flags = 1) C master has sent header byte (i2csr1.add10 and i2csr1.evf flags = 1) 70 evf add10 tra busy btf adsl m/sl sb 9
272/398 i2c bus interface i 2 c bus interface (contd) C address byte successfully transmitted in mas- ter mode. (i2csr1.evf = 1 and i2csr2.addtx=1) bit 6 = add10 10-bit addressing in master mode. this bit is set when the master has sent the first byte in 10-bit address mode. an interrupt is gener- ated if ite=1. it is cleared by software reading i2csr1 register followed by a write in the i2cdr register of the second address byte. it is also cleared by hard- ware when peripheral is disabled (i2ccr.pe=0) or when the stopf bit is set. 0: no add10 event occurred. 1: master has sent first address byte (header). bit 5 = tra transmitter/ receiver. when btf flag of this register is set and also tra=1, then a data byte has to be transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after the stopf flag of i2csr2 register is set, loss of bus arbitration (arlo flag of i2csr2 register is set) or when the interface is disabled (i2ccr.pe=0). 0: a data byte is received (if i2csr1.btf=1) 1: a data byte can be transmitted (if i2csr1.btf=1) bit 4 = busy bus busy . it indicates a communication in progress on the bus. the detection of the communications is al- ways active (even if the peripheral is disabled). this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. this information is still updated when the interface is disabled (i2ccr.pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or before the transmission of a data byte with interrupt generation if ite=1. it is cleared by software reading i2csr1 register followed by a read or write of i2cdr register or when dma is complete. it is also cleared by hardware when the interface is disabled (i2ccr.pe=0). C following a byte transmission, this bit is set after reception of the acknowledge clock pulse. btf is cleared by reading i2csr1 register followed by writing the next byte in i2cdr register or when dma is complete. C following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading i2csr1 reg- ister followed by reading the byte from i2cdr register or when dma is complete. the scl line is held low while i2csr1.btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware if the received slave ad- dress matches the i2coar1/i2coar2 register content or a general call address. an interrupt is generated if ite=1. it is cleared by software reading i2csr1 register or by hardware when the interface is disabled (i2ccr.pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (start condition generated on the lines after the i2ccr.start bit is set). it is cleared by hardware after detecting a stop condi- tion on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (i2ccr.pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write of start=1 if the bus is free). an interrupt is gener- ated if ite=1. it is cleared by software reading i2csr1 register followed by writing the address byte in i2cdr register. it is also cleared by hard- ware when the interface is disabled (i2ccr.pe=0). the scl line is held low while sb=1. 0: no start condition 1: start condition generated 9
273/398 i2c bus interface i 2 c bus interface (contd) i 2 c status register 2 (i2csr2) r242 - read only register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) note: some bits of this register are reset by a read operation of the register. care must be taken when using instructions that work on single bit. some of them perform a read of all the bits of the register before modifying or testing the wanted bit. so oth- er bits of the register could be affected by the op- eration. in the same way, the test/compare operations per- form a read operation. moreover, if some interrupt events occur while the register is read, the corresponding flags are set, and correctly read, but if the read operation resets the flags, no interrupt request occurs. bits 7:6 = reserved. forced to 0 by hardware. bit 5 = addtx address or 2nd header transmitted in master mode. this bit is set by hardware when the peripheral, enabled in master mode, has received the ac- knowledge relative to: C address byte in 7-bit mode C address or 2nd header byte in 10-bit mode. 0: no address or 2nd header byte transmitted 1: address or 2nd header byte transmitted. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading i2csr2 register after the falling edge of the acknowledge scl pulse , or by hardware when the interface is disa- bled (i2ccr.pe=0). the scl line is not held low while af=1. 0: no acknowledge failure detected 1: a data or address byte was not acknowledged bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge. an interrupt is generated if ite=1. it is cleared by software reading i2csr2 register or by hardware when the interface is disabled (i2ccr.pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected ( while slave receiver ) bit 2 = arlo arbitration lost . this bit is set by hardware when the interface (in master mode) loses the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by software reading i2csr2 register or by hardware when the interface is disabled (i2ccr.pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a start or stop condition during a byte trans- fer. an interrupt is generated if ite=1. it is cleared by software reading i2csr2 register or by hardware when the interface is disabled (i2ccr.pe=0). the scl line is not held low while berr=1. note : if a misplaced start condition is detected, also the arlo flag is set; moreover, if a misplaced stop condition is placed on the acknowledge scl pulse, also the af flag is set. 0: no start or stop condition detected during byte transfer 1: start or stop condition detected during byte transfer bit 0 = gcal general call address matched. this bit is set by hardware after an address matches with the value stored in the i2cadr reg- ister while engc=1. in the i2cadr the general call address must be placed before enabling the peripheral. it is cleared by hardware after the detection of a stop condition, or when the peripheral is disabled (i2ccr.pe=0). 0: no match 1: general call address matched. 70 0 0 addtx af stopf arlo berr gcal 9
274/398 i2c bus interface i 2 c bus interface (contd) i 2 c clock control register (i2cccr) r243 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is used to select between fast and stand- ard mode. see the description of the following bits. it is set and cleared by software. it is not cleared when the peripheral is disabled (i2ccr.pe=0) bits 6:0 = cc[6:0] 9-bit divider programming implementation of a programmable clock divider. these bits and the cc[8:7] bits of the i2ceccr register select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disa- bled (i2ccr.pe=0). C standard mode (fm/sm=0): f scl <= 100khz f scl = intclk/(2x([cc8..cc0]+2)) C fast mode (fm/sm=1): f scl > 100khz f scl = intclk/(3x([cc8..cc0]+2)) note: the programmed frequency is available with no load on scl and sda pins. i 2 c own address register 1 (i2coar1) r244 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) 7-bit addressing mode bits 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disa- bled (i2ccr.pe=0). bit 0 = add0 address direction bit. this bit is dont care; the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (i2ccr.pe=0). note: address 01h is always ignored. 10-bit addressing mode bits 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 cbus address of the interface. they are not cleared when the interface is disa- bled (i2ccr.pe=0). 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 add7 add6 add5 add4 add3 add2 add1 add0 9
275/398 i2c bus interface i 2 c bus interface (contd) i 2 c own address register 2 (i2coar2) r245 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) bits 7:6,4 = freq[2:0] frequency bits. important: to guarantee correct operation, set these bits before enabling the interface (while i2ccr.pe=0). these bits can be set only when the interface is disabled (i2ccr.pe=0). to configure the interface to i 2 c specified delays, select the value corre- sponding to the microcontroller internal frequency intclk. note: if an incorrect value, with respect to the mcu internal frequency, is written in these bits, the timings of the peripheral will not meet the i 2 c bus standard requirements. note: the freq[2:0] = 101, 110, 111 configura- tions must not be used. bit 5 = en10bit enable 10-bit i 2 cbus mode . when this bit is set, the 10-bit i 2 cbus mode is en- abled. this bit can be written only when the peripheral is disabled (i2ccr.pe=0). 0: 7-bit mode selected 1: 10-bit mode selected bits 4:3 = reserved. bits 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 cbus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (i2ccr.pe=0). bit 0 = reserved. i 2 c data register (i2cdr) r246 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) bits 7:0 = dr[7:0] i2c data. C in transmitter mode: i2cdr contains the next byte of data to be trans- mitted. the byte transmission begins after the microcontroller has written in i2cdr or on the next rising edge of the clock if dma is complete. C in receiver mode: i2cdr contains the last byte of data received. the next byte receipt begins after the i2cdr read by the microcontroller or on the next rising edge of the clock if dma is complete. general call address (i2cadr) r247 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 1010 0000 (a0h) bits 7:0 = adr[7:0] interface address . these bits define the i 2 cbus general call address of the interface. it must be written with the correct value depending on the use of the peripheral.if the peripheral is used in i 2 c bus mode, the 00h value must be loaded as general call address. the customer could load the register with other values. the bits can be written only when the peripheral is disabled (i2ccr.pe=0) the adr0 bit is dont care; the interface acknowl- edges either 0 or 1. note: address 01h is always ignored. 70 freq1 freq0 en10bit freq2 0 add9 add8 0 intclk range (mhz) freq2 freq1 freq0 2.5 - 6 0 0 0 6- 10 0 0 1 10- 14 0 1 0 14 - 30 0 1 1 30 - 50 1 0 0 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 9
276/398 i2c bus interface i 2 c bus interface (contd) interrupt status register (i2cisr) r248 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 1xxx xxxx (xxh) bit 7 = dmastop dma suspended mode . this bit selects between dma suspended mode and dma not suspended mode. in dma suspended mode, if the error interrupt pending bit (i2cisr.ierrp) is set, no dma re- quest is performed. dma requests are performed only when ierrp=0. moreover the error condi- tion interrupt source has a higher priority than the dma. in dma not-suspended mode, the status of ierrp bit has no effect on dma requests. moreo- ver the dma has higher priority with respect to oth- er interrupt sources. 0: dma suspended mode 1: dma not-suspended mode bits 6:4 = prl[2:0] interrupt/dma priority bits . the priority is encoded with these three bits. the value of 0 has the highest priority, the value 7 has no priority. after the setting of this priority lev- el, the priorities between the different interrupt/ dma sources is hardware defined according with the following scheme: C error condition interrupt (if dmastop=1) (high- est priority) C receiver dma request C transmitter dma request C error condition interrupt (if dmastop=0 C data received/receiver end of block C peripheral ready to transmit/transmitter end of block (lowest priority) bit 3 = reserved. must be cleared. bit 2 = ierrp error condition pending bit 0: no error 1: error event detected (if ite=1) note: depending on the status of the i2cisr.dmastop bit, this flag can suspend or not suspend the dma requests. note: the interrupt pending bits can be reset by writing a 0 but is not possible to write a 1. it is mandatory to clear the interrupt source by writing a 0 in the pending bit when executing the interrupt service routine. when serving an interrupt routine, the user should reset only the pending bit related to the served interrupt routine (and not reset the other pending bits). to detect the specific error condition that oc- curred, the flag bits of the i2csr1 and i2csr2 register should be checked. note: the ierrp pending bit is forced high when- the error event flags are set (adsl and sb flags in the i2csr1 register, sclf, addtx, af, stopf, arlo and berr flags in the i2csr2 register). if at least one flag is set, the application code should not reset the ierrp bit. bit 1 = irxp data received pending bit 0: no data received 1: data received (if ite=1). bit 0 = itxp peripheral ready to transmit pend- ing bit 0: peripheral not ready to transmit 1: peripheral ready to transmit a data byte (if ite=1). 70 dmastop prl2 prl1 prl0 0 ierrp irxp itxp 9
277/398 i2c bus interface i 2 c bus interface (contd) interrupt vector register (i2civr) r249 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: undefined bits 7:3 = v[7:3] interrupt vector base address . user programmable interrupt vector bits. these are the five more significant bits of the interrupt vector base address. they must be set before en- abling the interrupt features. bits 2:1 = ev[2:1] encoded interrupt source . these read-only bits are set by hardware accord- ing to the interrupt source: C 01: error condition detected C 10: data received C 11: peripheral ready to transmit bit 0 = reserved. forced by hardware to 0. receiver dma source address pointer register (i2crdap) r250 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: undefined bits 7:1 = ra[7:1] receiver dma address pointer . i2crdap contains the address of the pointer (in the register file) of the receiver dma data source when the dma is selected between the peripheral and the memory space. otherwise, (dma between peripheral and register file), this register has no meaning. see section 10.8.6.1 for more details on the use of this register. bit 0 = rps receiver dma memory pointer selec- tor . if memory has been selected for dma transfer (i2crdc.rf/mem = 0) then: 0: select isr register for receiver dma transfer address extension. 1: select dmasr register for receiver dma trans- fer address extension. receiver dma transaction counter register (i2crdc) r251 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: undefined bits 7:1 = rc[7:1] receiver dma counter pointer. i2crdc contains the address of the pointer (in the register file) of the dma receiver transaction counter when the dma between peripheral and memory space is selected. otherwise (dma be- tween peripheral and register file), this register points to a pair of registers that are used as dma address register and dma transaction counter. see section 10.8.6.1 and section 10.8.6.2 for more details on the use of this register. bit 0 = rf/mem receiver register file/ memory selector. 0: dma towards memory 1: dma towards register file 70 v7 v6 v5 v4 v3 ev2 ev1 0 70 ra7 ra6 ra5 ra4 ra3 ra2 ra1 rps 70 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rf/mem 9
278/398 i2c bus interface i 2 c bus interface (contd) transmitter dma source address pointer register (i2ctdap) r252 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: undefined bits 7:1= ta[7:1] transmit dma address pointer. i2ctdap contains the address of the pointer (in the register file) of the transmitter dma data source when the dma between the peripheral and the memory space is selected. otherwise (dma between the peripheral and register file), this reg- ister has no meaning. see section 10.8.6.2 for more details on the use of this register. bit 0 = tps transmitter dma memory pointer se- lector . if memory has been selected for dma transfer (i2ctdc.rf/mem = 0) then: 0: select isr register for transmitter dma transfer address extension. 1: select dmasr register for transmitter dma transfer address extension. transmitter dma transaction coun- ter register (i2ctdc) r253 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: undefined bits 7:1 = tc[7:1] transmit dma counter pointer . i2ctdc contains the address of the pointer (in the register file) of the dma transmitter transaction counter when the dma between peripheral and memory space is selected. otherwise, if the dma between peripheral and register file is selected, this register points to a pair of registers that are used as dma address register and dma transac- tion counter. see section 10.8.6.1 and section 10.8.6.2 for more details on the use of this register. bit 0 = rf/mem transmitter register file/ memo- ry selector. 0: dma from memory 1: dma from register file extended clock control register (i2ceccr) r254 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 0000 0000 (00h) bits 7:2 = reserved. must always be cleared. bits 1:0 = cc[8:7] 9-bit divider programming implementation of a programmable clock divider. these bits and the cc[6:0] bits of the i2cccr reg- ister select the speed of the bus (f scl ). for a description of the use of these bits, see the i2cccr register. they are not cleared when the interface is disa- bled (i2cccr.pe=0). 70 ta7 ta6 ta5 ta4 ta3 ta2 ta1 tps 70 tc7 tc6 tc5 tc4 tc3 tc2 tc1 rf/mem 70 0 0 0 0 0 0 cc8 cc7 9
279/398 i2c bus interface i 2 c bus interface (contd) interrupt mask register (i2cimr) r255 - read / write register page: 20 (i2c_0) or 22 (i2c_1) reset value: 00xx 0000 (x0h) bit 7 = rxdm receiver dma mask . 0: dma reception disable. 1: dma reception enable rxdm is reset by hardware when the transaction counter value decrements to zero, that is when a receiver end of block interrupt is issued. bit 6 = txdm transmitter dma mask . 0: dma transmission disable. 1: dma transmission enable. txdm is reset by hardware when the transaction counter value decrements to zero, that is when a transmitter end of block interrupt is issued. bit 5 = reobp receiver dma end of block flag . reobp should be reset by software in order to avoid undesired interrupt routines, especially in in- itialization routine (after reset) and after entering the end of block interrupt routine.writing 0 in this bit will cancel the interrupt request note: reobp can only be written to 0. 0: end of block not reached. 1: end of data block in dma receiver detected bit 4 = teobp transmitter dma end of block te- obp should be reset by software in order to avoid undesired interrupt routines, especially in initializa- tion routine (after reset) and after entering the end of block interrupt routine.writing 0 will cancel the interrupt request. note: teobp can only be written to 0. 0: end of block not reached 1: end of data block in dma transmitter detected. bit 3 = reserved. this bit must be cleared. bit 2 = ierrm error condition interrupt mask bit. this bit enables/ disables the error interrupt. 0: error interrupt disabled. 1: error interrupt enabled. bit 1 = irxm data received interrupt mask bit. this bit enables/ disables the data received and receive dma end of block interrupts. 0: interrupts disabled 1: interrupts enabled note: this bit has no effect on dma transfer bit 0 = itxm peripheral ready to transmit inter- rupt mask bit. this bit enables/ disables the peripheral ready to transmit and transmit dma end of block inter- rupts. 0: interrupts disabled 1: interrupts enabled note: this bit has no effect on dma transfer. 70 rxdm txdm reobp teobp 0 ierrm irxm itxm 9
280/398 i2c bus interface i 2 c bus interface (contd) table 51. i 2 c bus register map and reset values address (hex.) register name 765 4 3210 f0h i2ccr reset value - 0 - 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 f1h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 f2h i2csr2 reset value - 0 0 0 addtx 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 f3h i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 f4h i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 f5h i2coar2 reset value freq1 0 freq0 0 en10bit 0 freq2 0 0 0 add9 0 add8 0 0 0 f6h i2cdr reset value dr7 0 dr6 0 dr5 0 dr4 0 dr3 0 dr2 0 dr1 0 dr0 0 f7h i2cadr reset value adr7 1 adr6 0 adr5 1 adr4 0 adr3 0 adr2 0 adr1 0 adr0 0 f8h i2cisr reset value dmastop 1 prl2 x prl1 x prl0 xx ierrp x irxp x itxp x f9h i2civr reset value v7 x v6 x v5 x v4 x v3 x ev2 x ev1 x 0 0 fah i2crdap reset value ra7 x ra6 x ra5 x ra4 x ra3 x ra2 x ra1 x rps x fbh i2crdc reset value rc7 x rc6 x rc5 x rc4 x rc3 x rc2 x rc1 x rf/mem x fch i2ctdap reset value ta7 x ta6 x ta5 x ta4 x ta3 x ta2 x ta1 x tps x fdh i2ctdc reset value tc7 x tc6 x tc5 x tc4 x tc3 x tc2 x tc1 x rf/mem x feh i2ceccr 0 0 0 0 0 0 0 0 0 0 0 0 cc8 0 cc7 0 ffh i2cimr reset value rxdm 0 txdm 0 reobp x teobp x0 ierrm 0 irxm 0 itxm 0 9
281/398 j1850 byte level protocol decoder (jblpd) 10.9 j1850 byte level protocol decoder (jblpd) 10.9.1 introduction the jblpd is used to exchange data between the st9 microcontroller and an external j1850 trans- ceiver i.c. the jblpd transmits a string of variable pulse width (vpw) symbols to the transceiver. it also re- ceives vpw encoded symbols from the transceiv- er, decodes them and places the data in a register. in-frame responses of type 0, 1, 2 and 3 are sup- ported and the appropriate normalization bit is generated automatically. the jblpd filters out any incoming messages which it does not care to receive. it also includes a programmable external loop delay. the jblpd uses two signals to communicate with the transceiver: C vpwi (input) C vpwo (output) 10.9.2 main features n sae j1850 compatible n digital filter n in-frame responses of type 0, 1, 2, 3 supported with automatic normalization bit n programmable external loop delay n diagnostic 4x time mode n diagnostic local loopback mode n wide range of mcu internal frequencies allowed n low power consumption mode (jblpd suspended) n very low power consumption mode (jblpd disabled) n dont care message filter n selectable vpwi input polarity n selectable normalization bit symbol form n 6 maskable interrupts n dma transmission and reception with end of block interrupts 9
282/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) figure 125. jblpd byte level protocol decoder block diagram i.d. filter freg[0:31] rxdata txdata paddr crc\ byte crc byte mux vpw encoder digital filter vpw decoder crc generator arbitration checker jblpd state machine status error control options txop clksel interrupt & dma logic and registers clock prescaler vpwi vpwo prescaled clock (encoder/decoder clock) loopback logic vpwi_loop vpwo_loop pin pin 9
283/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.3 functional description 10.9.3.1 j1850 protocol symbols j1850 symbols are defined as a duration (in micro- seconds or clock cycles) and a state which can be either an active state (logic high level on vpwo) or a passive state (logic low level on vpwo). an idle j1850 bus is in a passive state. any symbol begins by changing the state of the vpw line. the line is in this state for a specific du- ration depending on the symbol being transmitted. durations, and hence symbols, are measured as time between successive state transitions. each symbol has only one level transition of a specific duration. symbols for logic zero and one data bits can be ei- ther a high or a low level, but all other symbols are defined at only one level. each symbol is placed directly next to another. therefore, every level transition means that anoth- er symbol has begun. data bits of a logic zero are either a short duration if in a passive state or a long duration if in an active state. data bits of a logic one are either a long du- ration if in a passive state or a short duration if in an active state. this ensures that data logic zeros predominate during bus arbitration. an eight bit data byte transmission will always have eight transitions. for all data byte and crc byte transfers, the first bit is a passive state and the last bit is an active state. for the duration of the vpw, symbols are ex- pressed in terms of tvs (or vpw mode timing val- ues). j1850 symbols and tv values are described in the sae j1850 specification, in table 52 and in table 53 . an ignored tv i.d. occurs for level transitions which occur in less than the minimum time re- quired for an invalid bit detect. the vpw encoder does not recognize these characters as they are filtered out by the digital filter. the vpw decoder does not resynchronize its counter with either edge of ignored pulses. therefore, the counter which times symbols continues to time from the last transition which occurred after a valid symbol (including the invalid bit symbol) was recognized. a symbol recognized as an invalid bit will resyn- chronize the vpw decoder to the invalid bit edges. in the case of the reception of an invalid bit, the jblpd peripheral will set the ibd bit in the er- ror register. the jblpd peripheral shall termi- nate any transmissions in progress, and disable receive transfers and rdrf flags until the vpw decoder recognizes a valid eof symbol from the bus. the jblpds state machine handles all the tv l.d.s in accordance with the sae j1850 specifica- tion. note: depending on the value of a control bit, the polarity of the vpwi input can be the same as the j1850 bus or inverted with respect to it. table 52. j1850 symbol definitions table 53. j1850 vpw mode timing value (tv) definitions (in clock cycles) symbol definition data bit zero passive for tv1 or ac- tive for tv2 data bit one passive for tv2 or ac- tive for tv1 start of frame (sof) active for tv3 end of data (eod) passive for tv3 end of frame (eof) passive for tv4 inter frame separation (ifs) passive for tv6 idle bus condition (idle) passive for > tv6 normalization bit (nb) active for tv1 or tv2 break (brk) active for tv5 pulse width or tv i.d. minimum duration nominal duration maximum duration ignored 0 n/a <=7 invalid bit >7 n/a <=34 tv1 >34 64 <=96 tv2 >96 128 <=163 tv3 >163 200 <=239 tv4 >239 280 n/a tv5 >239 300 n/a tv6 >280 300 n/a 9
284/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.3.2 transmitting messages this section describes the general procedures used by the jblpd to successfully transmit j1850 frames of data out the vpwo pin. the first five sub-sections describe the procedures used for transmitting the specific transmit data types. the last section goes into the details of the transmitted symbol timing, synchronizing of symbols received from the external j1850 bus, and how data bit ar- bitration works. the important concept to note for transmitting data is: the activity sent over the vpwo line should be timed with respect to the levels and transitions seen on the filtered vpwi line. the j1850 bus is a multiplexed bus, and the vpwo & vpwi pins interface to this bus through a transceiver i.c. therefore, the propagation delay through the transceiver i.c. and external bus filter- ing must be taken into account when looking for transmitted edges to appear back at the receiver. the external propagation delay for an edge sent out on the vpwo line, to be detected on the vpwi line is denoted as t p-ext and is programmable be- tween 0 and 31 s nominal via the jdly[4:0] bits in control register. the transmitter vpw encoder sets the proper level to be sent out the vpwo line. it then waits for the corresponding level transition to be reflected back at the vpw decoder input. taking into account the external loop delay (t p-ext ) and the digital filter delay, the encoder will time its output to remain at this level so that the received symbol is at the correct nominal symbol time (refer to transmit opcode queuing section). if arbitra- tion is lost at any time during bit 0 or bit 1 transmis- sion, then the vpwo line goes passive. at the end of the symbol time on vpwo, the encoder chang- es the state of vpwo if any more information is to be transmitted. it then times the new state change from the receiver decoder output. note that depending on the symbol (especially the sof, nb0, nb1 symbols) the decoder output may actually change to the desired state before the transmit is attempted. it is important to still syn- chronize off the decoder output to time the vpwo symbol time. a detailed description of the jblpd opcodes can be find in the description of the op[2:0] bits in the txop register. message byte string transmission (type 0 ifr) message byte transmitting is the outputting of data bytes on the vpwo pin that occurs subsequent to a received bus idle condition. all message byte strings start with a sof symbol transmission, then one or more data bytes are transmitted. a crc byte is then transmitted followed by an eod sym- bol (see figure 126 ) to complete the transmission. if transmission is queued while another frame is being received, then the jblpd will time an inter- frame separation (ifs) time (tv6) before com- mencing with the sof character. the user program will decide at some point that it wants to initiate a message byte string. the user program writes the txdata register with the first message data byte to be transmitted. next, the txop register is written with the msg opcode if more than one data byte is contained within the message, or with msg+crc opcode if one data byte is to be transmitted. the action of writing the txop register causes the trdy bit to be cleared signifying that the txdata register is full and a corresponding opcode has been queued. the jblpd must wait for an eof nominal time period at which time data is transferred from the txdata register to the transmit shift register. the trdy bit is again set since the txdata register is empty. the jblpd should also begin transmission if an- other device begins transmitting early. as long as an eof minimum time period elapses, the jblpd should begin timing and asserting the sof symbol with the intention of arbitrating for the bus during the transmission of the first data byte. if a transmit is requested during an incoming sof symbol, the jblpd should be able to synchronize itself to the incoming sof up to a time of tv1 max. (96 s) into the sof symbol before declaring that it was too late to arbitrate for this frame. 9
285/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) if the j1850 bus was idle at the time the first data byte and opcode are written, the transmitter will immediately transfer data from the txdata regis- ter to the transmit shift register. the trdy bit will once again be set signifying the readiness to ac- cept a new data byte. the second data byte can then be written followed by the respective opcode. in the case of the last data byte, the txop register should be written with the msg+crc opcode. the transmitter will transmit the internally generated crc after the last bit of the data byte. once the trdy bit is set signifying the acceptance of the last data byte, the first byte of the next message can be queued by writing the txdata register fol- lowed by a txop register write. the block will wait until the current data and the crc data byte are sent out and a new ifs has expired before trans- mitting the new data. this is the case even if ifr data reception takes place in the interim. lost arbitration any time during the transfer of type 0 data will be honoured by immediately relinquish- ing control to the higher priority message. the tla bit in the status register is set accordingly and an interrupt will be generated assuming the tla_m bit in the imr register is set. it is responsi- bility of the user program to re-send the message beginning with the first byte if desired. this may be done at any time by rewriting only the txop regis- ter if the txdata contents have not changed. any transmitted data and crc bytes during the transmit frame will also be received and trans- ferred to the rxdata register if the corresponding message filter bit is set in the freg[0:31] regis- ters. if the corresponding bit is not set in freg[0:31], then the transmitted data is also not transferred to rxdata. also, the rdrf will not get set during frame and receive events such as rdof & eodm. note: the correct procedure for transmitting is to write first the txdata register and then the txop register except during dma transfers (see section 10.9.6.4 dma management in transmission mode ). transmitting a type 1 ifr the user program will decide to transmit an ifr type 1 byte in response to a message which is cur- rently being received (see figure 127 ). it does so by writing the ifr1 opcode to the txop register. transmitting ifr data type 1 requires only a single write of the txop register with the ifr1 opcode set. the mlc[3:0] bits should be set to the proper byte-received-count-required-before-ifring val- ue. if no error conditions (ibd, ifd, tra, rbrk or crce) exist to prevent transmission, the jblpd peripheral will then transmit out the contents of the paddr register at the next eod nominal time pe- riod or at a time greater than the eod minimum time period if a falling edge is detected on filtered j1850 bus line signifying another transmitter is be- ginning early. the nb1 symbol precedes the pad- dr register value and is followed with an eof de- limiter. the trdy flag is cleared on the write of the txop register. the trdy bit is set once the nb1 begins transmitting. although the jblpd should never lose arbitration for data in the ifr portion of a type 1 frame, higher priority messages are always honoured under the rules of arbitration. if arbitration is lost then the vpwo line is set to the passive state. the tla bit in the status register is set accordingly and an interrupt will be generated if enabled. the ifr1 is not retried. it is lost if the jblpd peripheral loses arbitration. also, the data that made it out on the bus will be received in the rxdata register if not put into sleep mode. note that for the transmitter to synchronize to the incoming signals of a frame, an ifr should be queued before an eodm is re- ceived for the present frame. 9
286/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) transmitting a type 2 ifr the user program will decide to transmit an ifr type 2 byte in response to a message which is cur- rently being received (see figure 128 ). it does so by writing the ifr2 opcode to the txop register. transmitting ifr data type 2 requires only a single write of the txop register with the ifr2 opcode set. the mlc[3:0] bits can also be set to check for message length errors. if no error conditions (ibd, ifd, tra, rbrk or crce) exist to prevent trans- mission, the jblpd will transmit out the contents of the paddr register at the next eod nominal time period or after an eod minimum time period if a rising edge is detected on the filtered vpwi line signifying another transmitter beginning early. the nb1 symbol precedes the paddr register value and is followed with an eof delimiter. the trdy flag will be cleared on the write of the txop regis- ter. the trdy bit is set once the nb1 begins transmitting. lost arbitration for this case is a normal occur- rence since type 2 ifr data is made up of single bytes from multiple responders. if arbitration is lost the vpwo line is released and the jblpd waits until the byte on the vpwi line is completed. note that the ifr that did make it out on the bus will be received in the rxdata register if it is not put into sleep mode. then, the jblpd re-attempts to send its physical address immediately after the end of the last byte. the tla bit is not set if arbitration is lost and the user program does not need to re- queue data or an opcode. the jblpd will re-at- tempt to send its paddr register contents until it successfully does so or the 12-byte frame maxi- mum is reached if nfl=0. if nfl=1, then re-at- tempts to send an lfr2 are executed until can- celled by the cancel opcode or a jblpd disa- ble. note that for the transmitter to synchronize to the incoming signals of a frame, an ifr should be queued before an eodm is received for the present frame. transmitting a type 3 lfr data string the user program will decide to transmit an ifr type 3 byte string in response to a message which is currently being received (see figure 129 ). it does so by writing the ifr3 or ifr3+crc opcode to the txop register. transmitting ifr data type 3 is similar to transmitting a message, in that the tx- data register is written with the first data byte fol- lowed by a txop register write. for a single data byte ifr3 transmission, the txop register would be written with ifr3+crc opcode set. the mlc[3:0] bits can also be set to a proper value to check for message length errors before enabling the ifr transmit. if no error conditions (ibd, ifd, tra, rbrk or crce) exist to prevent transmission, the jblpd will wait for an eod nominal time period on the fil- tered vpwi line (or for at least an eod minimum time followed by a rising edge signifying another transmitter beginning early) at which time data is transferred from the txdata register to the trans- mit shift register. the trdy bit is set since the tx- data register is empty. a nb0 symbol is output on the vpwo line followed by the data byte and possibly the crc byte if a ifr3+crc opcode was set. once the first ifr3 byte has been successfully transmitted, successive ifr3 bytes are sent with txdata/txop write sequences where the mlc[3:o] bits are dont cares. the final byte in the ifr3 string must be transmitted with the ifr3+crc opcode to trigger the jblpd to ap- pend the crc byte to the string. the user program may queue up the next message opcode se- quence once the trdy bit has been set. although arbitration should never be lost for data in the ifr portion of a type 3 frame, higher priority messages are always honoured under the rules of arbitration. if arbitration is lost then the block should relinquish the bus by taking the vpwo line to the passive state. in this case the tla bit in the status register is set, and an interrupt will be generated if enabled. note also, that the ifr data that did make it out on the bus will be received in the rxdata register if not in sleep mode. note that for the transmitter to synchronize to the in- coming signals of a frame, an ifr should be queued before an eodm is received for the cur- rent frame. 9
287/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) figure 126. j1850 string transmission type 0 figure 127. j1850 string transmission type 1 figure 128. j1850 string transmission type 2 figure 129. j1850 string transmission type 3 i.d. byte data byte(s) (if any) crc sof eof message frame i.d. byte data byte(s) (if any) crc sof eod message rxd from another node frame nb1 ifr byte eof ifr to be sent i.d. byte data byte(s) (if any) crc sof eod message rxd from another node frame nb1 ifr byte eof ifr to be sent ifr byte ... ... i.d. byte data byte(s) (if any) crc sof eod message rxd from another node frame nb0 ifr data byte(s) eof ifr to be sent crc byte 9
288/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) transmit opcode queuing the jblpd has the capability of queuing opcode transmits written to the txop register until j1850 bus conditions are in a correct state for the trans- mit to occur. for example, a msgx opcode can be queued when the jblpd is presently receiving a frame (or transmitting a msg+crc opcode) or an ifrx opcode can be queued when currently re- ceiving or transmitting the message portion of a frame. queuing a msg or msg+crc opcode for the next frame can occur while another frame is in progress. a msgx opcode is written to the txop register when the present frame is past the point where arbitration for control of the bus for this frame can occur. the jblpd will wait for a nomi- nal ifs symbol (or eofmin if another node begins early) to appear on the vpwi line before com- mencing to transmit this queued opcode. the trdy bit for the queued opcode will remain clear until the eofmin is detected on the vpwi line where it will then get set. queued msgx transmits for the next frame do not get cancelled for tla, ibd, ifd or crce errors that occur in the present frame. an rbrk error will cancel a queued op- code for the next frame. queuing an ifrx opcode for the present frame can occur at any time after the detection of the be- ginning of an sof character from the vpwi line. the queued ifr will wait for a nominal eod sym- bol (or eodmin if another node begins early) be- fore commencing to transmit the ifr. a queued ifr transmit will be cancelled on ibd, lfd, crce, rbrk errors as well as on a correct message length check error or frame length limit violation if these checks are enabled. transmit bus timing, arbitration, and syn- chronization the external j1850 bus on the other side of the transceiver i.c. is a single wire multiplex bus with multiple nodes transmitting a number of different types of message frames. each node can transmit at any time and synchronization and arbitration is used to determine who wins control of the trans- mit. it is the obligation of the jblpd transmitter section to synchronize off of symbols on the bus, and to place only nominal symbol times onto the bus within the accuracy of the peripheral (+/- 1 s). to transmit proper symbols the jblpd must know what is going on out on the bus. fortunately, the jblpd has a receiver pin which tells the transmit- ter about bus activity. due to characteristics of the j1850 bus and the eight-clock digital filter, the sig- nals presented to the vpw symbol decoder are delayed a certain amount of time behind the actual j1850 bus. also, due to wave shaping and other signal conditioning of the transceiver i.c. the ac- tions of the vpwo pin on the transmitter take time to appear on the bus itself. the total external j1850 bus delays are defined in the sae j1850 standard as nominally 16 s. the nominal 16 s loop delay will actually vary between different transceiver i.cs. the jblpd peripheral thus in- cludes a programmability of the external loop de- lay in the bit positions jdly[4:0]. this assures only nominal transmit symbols are placed on the bus by the jblpd. the method of transmitting for the jblpd includes interaction between the transmitter and the receiv- er. the transmitter starts a symbol by placing the proper level (active or passive) on its vpwo pin. the transmitter then waits for the corresponding pin transition (inverted, of course) at the vpw de- coder input. note that the level may actually ap- pear at the input before the transmitter places the value on the vpwo pin. timing of the remainder of the symbol starts when the transition is detect- ed. refer to figure 131 , case 1. the symbol time- out value is defined as: symboltimeout = nominalsymboltime - externalloop- delay - 8 s nominalsymboltime = tv symbol time externalloopdelay = defined via jdly[4:0] 8 s = digital filter bit-by-bit arbitration must be used to settle the conflicts that occur when multiple nodes attempt to transmit frames simultaneously. arbitration is ap- plied to each data bit symbol transmitted starting after the sof or nbx symbol and continuing until the eod symbol. during simultaneous transmis- sions of active and passive states on the bus, the resultant state on the bus is the active state. if the jblpd detects a received symbol from the bus that is different from the symbol being transmitted, then the jblpd will discontinue its transmit opera- tion prior to the start of the next bit. once arbitra- tion has been lost, the vpwo pin must go passive within one period of the prescaled clock of the pe- ripheral. figure 130 shows 3 nodes attempting to arbitrate for the bus with node b eventually win- ning with the highest priority data. 9
289/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) figure 130. j1850 arbitration example figure 131. j1850 received symbol timing transmitting node a transmitting node b transmitting node c signal on bus active passive active passive active passive active passive sof 0 0 110 001 sof 0 0 110 00 0 sof 0 0 110 1 sof 0 0 110 00 0 case 1 vpwo vpwi vpw decoder case 2 vpwo tx2 vpwi vpw decoder case 3 vpwo tx2 vpwi vpw decoder 178 s 178 s 178 s 822 -6 014 192 200 208 214 222 9
290/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) use of symbol and bit synchronization is an inte- gral part of the j1850 bus scheme. therefore, tight coupling of the encoder and decoder functions is required to maintain synchronization during trans- mits. transmitted symbols and bits are initiated by the encoder and are timed through the decoder to realize synchronization. figure 131 exemplifies synchronization with 3 examples for an sof sym- bol and jdly[4:0] = 01110b. case 1 shows a single transmitter arbitrating for the bus. the vpwo pin is asserted, and 14s later the bus transitions to an active state. the 14s de- lay is due to the nominal delay through the exter- nal transceiver chip. the signal is echoed back to the transceiver through the vpwi pin, and pro- ceeds through the digital filter. the digital filter has a loop delay of 8 clock cycles with the signal finally presented to the decoder 22 s after the vpwo pin was asserted. the decoder waits 178 s be- fore issuing a signal to the encoder signifying the end of the symbol. the vpwo pin is de-asserted producing the nominal sof bit timing (22 s + 178s = 200 s). case 2 shows a condition where 2 transmitters at- tempt to arbitrate for the bus at nearly the same time with a second transmitter, tx2, beginning slightly earlier than the vpwo pin. since the jblpd always times symbols from its receiver perspective, 178s after the decoder sees the ris- ing edge it issues a signal to the encoder to signify the end of the sof. nominal sof timings are maintained and the jblpd re-synchronizes to tx2. case 3 again shows an example of 2 transmitters attempting to arbitrate for the bus at nearly the same time with the vpwo pin starting earlier than tx2. in this case tx2 is required to re-synchronize to vpwo. all 3 examples exemplify how bus timings are driv- en from the receiver perspective. once the receiv- er detects an active bus, the transmitter symbol timings are timed minus the transceiver and digital filter delays (i.e. sof = 200 s - 14s - 8s = 178s). this synchronization and timing off of the vpwi pin occurs for every symbol while transmit- ting. this ensures true arbitration during data byte transmissions. 10.9.3.3 receiving messages data is received from the external analog trans- ceiver on the vpwi pin. vpwi data is immediately passed through a digital filter that ignores all puls- es that are less than 7s. pulses greater than or equal to 7s and less than 34s are flagged as invalid bits (ibd) in the error register. once data passes through the filter, all delimiters are stripped from the data stream and data bits are shifted into the receive shift register by the decod- er logic. the first byte received after a valid sof character is compared with the flags contained in freg[0:31]. if the compare indicates that this message should be received, then the receive shift register contents are moved to the receive data register (rxdata) for the user program to access. the receive data register full bit (rdrf) is set to indicate that a complete byte has been received. for each byte that is to be received in a frame, once an entire byte has been received, the receive shift register contents are moved to the receive data register (rxdata). all data bits re- ceived, including crc bits, are transferred to the rxdata register. the receive data register full bit (rdrf) is set to indicate that a complete byte has been received. if the first byte after a valid sof indicates non-re- ception of this frame, then the current byte in the receive shift register is inhibited from being trans- ferred to the rxdata register and the rdrf flag remains clear (see the received message filter- ing section). also, no flags associated with receiv- ing a message (rdof, crce, ifd, ibd) are set. a crc check is kept on all bytes that are trans- ferred to the rxdata register during message byte reception (succeeding an sof symbol) and ifr3 reception (succeeding an nb0 symbol). the crc is initialized on receipt of the first byte that follows an sof symbol or an nb0 symbol. the crc check concludes on receipt of an eodm symbol. the crc error bit (crce), therefore, gets set after the eodm symbol has been recognized. refer to the sae recommended practice - j1850 manual for more information on crcs. 9
291/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) received message filtering the freg[0:31] registers can be considered an array of 256 bits (the freg[0].0 bit is bit 0 of the array and the freg[31].7 bit is bit 255). the i.d. byte of a message frame is used as a pointer to the array (see figure 132 ). upon the start of a frame, the first data byte re- ceived after the sof symbol determines the i.d. of the message frame. this i.d. byte addresses the i.d. byte flags stored in registers freg[0:31]. this operation is accomplished before the transfer of the i.d. byte into the rxdata register and before the rdrf bit is set. if the corresponding bit in the message filter array, freg[0:31], is set to zero (0), then the i.d. byte is not transferred to the rxdata register and the rdrf bit is not set. also, the remainder of the message frame is ignored until reception of an eofmin symbol. a received eofmin symbol ter- minates the operation of the message filter and enables the receiver for the next message. none of the flags related to the receiver, other than idle, are set. the eodm flag does not get set during a filtered frame. no error flags other than rbrk can get set. if the corresponding bit in the message filter array, freg[0:31], is set to a one (1), then the i.d. byte is transferred to the rxdata register and the rdrf is set. also, the remainder of the message is received unless sleep mode is invoked by the user program. all receiver flags and interrupts function normally. note that a break symbol received during a filtered out message will still be received. note also that the filter comparison occurs after reception of the first byte. so, any receive errors that occur before the message filter comparison (i.e. ibd, ifd) will be active at least until the filter comparison. transmitted message filtering when transmitting a message, the corresponding freg[0:31] i.d. filter bit may be set or cleared. if set, then the jblpd will receive all data informa- tion transferred during the frame, unless sleep mode is invoked. everything the jblpd transmits will be reflected in the rxdata register. because the jblpd has invalid bit detect (ibd), invalid frame detect (ifd), transmitter lost arbitra- tion (tra), and cyclic redundancy check error (crce) it is not necessary for the transmitter to lis- ten to the bytes that it is transmitting. the user may wish to filter out the transmitted messages from the receiver. this can reduce interrupt bur- den. when a transmitted i.d. byte is filtered by the receiver section of the block, then rdrf, rdof, eodm flags are inhibited and no rxdata trans- fers occur. the other flags associated normally with receiving - rbrk, crce, ifd, and ibd - are not inhibited, and they can be used to ascertain the condition of the message transmit. figure 132. i.d. byte and message filter array use i.d. byte value = n bit 0 = freg[0].0 bit 1 = freg[0].1 bit 2 = freg[0].2 bit 3 = freg[0].3 bit 4 = freg[0].4 bit n bit 254 = freg[31].6 bit 255 = freg[31].7 bit n+1 bit n-1 9
292/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.3.4 sleep mode sleep mode allows the user program to ignore the remainder of a message. normally, the user pro- gram can recognise if the message is of interest from the header bytes at the beginning of the mes- sage. if the user program is not interested in the message it simply writes the slp bit in the prlr register. this causes all additional data on the bus to be ignored until an eof minimum occurs. no additional flags (but not the eofm flag) and, there- fore, interrupts are generated for the remainder of the message. the single exception to this is a re- ceived break symbol while in sleep mode. break symbols always take precedence and will set the rbrk bit in the error register and generate an interrupt if the err_m bit in imr is set. sleep mode and the slp bit gets cleared on reception of an eof or break symbol. writes to the slp bit will be ignored if: 1) a valid eofm symbol was the last valid symbol detected, and 2) the j1850 bus line (after the filter) is passive. therefore, sleep mode can only be invoked after the sof symbol and subsequent data has been received, but before a valid eof is detected. if sleep mode is invoked within this time window, then any queued ifr transmit is aborted. if a msg type is queued and sleep mode is invoked, then the msg type will remain queued and an attempt to transmit will occur after the eof period has elapsed as usual. if slp mode is invoked while the jblpd is current- ly transmitting, then the jblpd effectively inhibits the rdrf, rdt, eodm, & rdof flags from being set, and disallows rxdata transfers. but, it other- wise functions normally as a transmitter, still allow- ing the trdy, tla, tto, tduf, tra, ibd, ifd, and crce bits to be set if required. this mode al- lows the user to not have to listen while talking. 10.9.3.5 normalization bit symbol selection the form of the nb0/nb1 symbol changes de- pending on the industry standard followed. a bit (nbsyms) in the options register selects the symbol timings used. refer to table 54 . 10.9.3.6 vpwi input line management the jblpd is able to work with j1850 transceiver chips that have both inverted and not inverted rx signal. a dedicated bit (inpol) of the options register must be programmed with the correct val- ue depending on the polarity of the vpwi input with respect to the j1850 bus line. refer to the in- pol bit description for more details. 10.9.3.7 loopback mode the jblpd is able to work in loopback mode. this mode, enabled setting the loopb bit of the op- tions register, internally connects the output sig- nal (vpwo) of the jblpd to the input (vpwi) without polarity inversion. the external vpwo pin of the mcu is forced in its passive state and the external vpwi pin is ignored (refer to figure 133 ). note: when the loopb bit is set or reset, edges could be detected by the j1850 decoder on the in- ternal vpwi line. these edges could be managed by the jblpd as j1850 protocol errors. it is sug- gested to enable/disable loopb when the jblpd is suspended (control.je=0, con- trol.jdis=0) or when the jblpd is disabled (control.jdis=1). table 54. normalization bit configurations symbol nbsyms=0 nbsyms=1 ifr with crc nb0 active tv2 (active long) active tv1 (active short) ifr without crc nb1 active tv1 (active short) active tv2 (active long) 9
293/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) figure 133. local loopback structure 10.9.3.8 peripheral clock management to work correctly, the encoder and decoder sec- tions of the peripheral need an internal clock at 1mhz. this clock is used to evaluate the protocol symbols timings in transmission and in reception. the prescaled clock is obtained by dividing the mcu internal clock frequency. the clksel regis- ter allows the selection of the right prescaling fac- tor. the six least significant bits of the register (freq[5:0]) must be programmed with a value us- ing the following formula: mcu internal freq. = 1mhz * (freq[5:0] + 1). note: if the mcu internal clock frequency is lower than 1mhz, the jblpd is not able to work correct- ly. if a frequency lower than 1mhz is used, the user program must disable the jblpd. note: when the mcu internal clock frequency or the clock prescaler factor are changed, the jblpd could lose synchronization with the j1850 bus. passive state vpwo from the peripheral logic vpwi toward the j1850 decoder polarity manager options.inpol options.loopb mcu vpwo pin mcu vpwi pin jblpd peripheral mcu 9
294/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.4 peripheral functional modes the jblpd can be programmed in 3 modes, de- pending on the value of the je and jdis bits in the control register, as shown in table 55 . table 55. jblpd functional modes depending on the mode selected, the jblpd is able or unable to transmit or receive messages. moreover the power consumption of the peripheral is affected. note : the configuration with both je and jdis set is forbidden. 10.9.4.1 jblpd enabled when the jblpd is enabled (control.je=1), it is able to transmit and receive messages. every feature is available and every register can be writ- ten. 10.9.4.2 jblpd suspended (low power mode) when the jblpd is suspended (control.je=0 and control.jdis=0), all the logic of the jblpd is stopped except the decoder logic. this feature allows a reduction of power consump- tion when the jblpd is not used, even if the de- coder is able to follow the bus traffic. so, at any time the jblpd is enabled, it is immediately syn- chronized with the j1850 bus. note : while the jblpd is suspended, the sta- tus register, the error register and the slp bit of the prlr register are forced into their reset val- ue. 10.9.4.3 jblpd disabled (very low power mode) setting the jdis bit in the control register, the jblpd is stopped until the bit is reset by software. also the j1850 decoder is stopped, so the jblpd is no longer synchronized with the bus. when the bit is reset, the jblpd will wait for a new idle state on the j1850 bus. this mode can be used to mini- mize power consumption when the jblpd is not used. note : while the jdis bit is set, the status regis- ter, the error register, the imr register and the slp, teobp and reobp bits of the prlr regis- ter are forced to their reset value. note: in order that the jdis bit is able to reset the imr register and the teobp and reobp bits, the jdis bit must be left at 1 at least for 6 mcu clock cycles (3 nops). note : the je bit of control register cannot be set with the same instruction that reset the jdis bit. it can be set only after the jdis bit is reset. je jdis mode 0 1 jblpd disabled 0 0 jblpd suspended 1 0 jblpd enabled 9
295/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.5 interrupt features the jblpd has six interrupt sources that it han- dles using the internal interrupts protocol. other two interrupt sources (reob and teob) are relat- ed to the dma feature (see section 10.9.6 dma features ). no external interrupt channel is used by the jblpd. the dedicated registers of the jblpd should be loaded with appropriate values to set the interrupt vector (see the description of the ivr register), the interrupt mask bits (see the description of the imr register) and the interrupt pending bits (see the de- scription of the status and prlr registers). the interrupt sources are as follows: C the error interrupt is generated when the er- ror bit of the status register is set. this bit is set when the following events occur: trans- mitter timeout, transmitter data underflow, receiver data overflow, transmit request aborted, received break symbol, cyclic re- dundancy check error, invalid frame detect, invalid bit detect (a more detailed description of these events is given in the description of the error register). C the tla interrupt is generated when the trans- mitter loses the arbitration (a more detailed de- scription of this condition is given in the tla bit description of the status register). C the eodm interrupt is generated when the jblpd detects a passive level on the vpwi line longer than the minimum time accepted by the standard for the end of data symbol (a more detailed description of this condition is given in the eodm bit description of the status regis- ter). C the eofm interrupt is generated when the jblpd detects a passive level on the vpwi line longer than the minimum time accepted by the standard for the end of frame symbol (a more detailed description of this condition is given in the eofm bit description of the status regis- ter). C the rdrf interrupt is generated when a com- plete data byte has been received and placed in the rxdata register (see also the rdrf bit description of the status register). C the reob (receive end of block) interrupt is generated when receiving using dma and the last byte of a sequence of data is read from the jblpd. C the trdy interrupt is generated by two condi- tions: when the txop register is ready to ac- cept a new opcode for transmission; when the transmit state machine accepts the opcode for transmission (a more detailed description of this condition is given in the trdy bit description of the status register). C the teob (transmit end of block) interrupt is generated when transmitting using dma and the last byte of a sequence of data is written to the jblpd. 10.9.5.1 interrupt management to use the interrupt features the user has to follow these steps: C set the correct priority level of the jblpd C set the correct interrupt vector C reset the pending bits C enable the required interrupt source note : it is strongly recommended to reset the pending bits before un-masking the related inter- rupt sources to avoid spurious interrupt requests. the priority with respect the other st9 peripherals is programmable by the user setting the three most significant bits of the interrupt priority level register (prlr). the lowest interrupt priority is ob- tained by setting all the bits (this priority level is never acknowledged by the cpu and is equivalent to disabling the interrupts of the jblpd); the high- est interrupt priority is programmed resetting the bits. see the interrupt and dma chapters of the datasheet for more details. when the jblpd interrupt priority is set, the prior- ity between the internal interrupt sources is fixed by hardware as shown in table 56 . 9
296/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) note : after an mcu reset, the dma requests of the jblpd have a higher priority than the interrupt requests. if the dmasusp bit of the options register is set, while the error and tla flags are set, no dma transfer will be performed, allowing the re- lavent interrupt routines to manage each condition and, if necessary, disable the dma transfer (refer to section 10.9.6 dma features ). table 56. jblpd internal priority levels the user can program the most significant bits of the interrupt vectors by writing the v[7:3] bits of the ivr register. starting from the value stored by the user, the jblpd sets the three least significant bits of the ivr register to produce four interrupt vectors that are associated with interrupt sources as shown in table 57 . table 57. jblpd interrupt vectors each interrupt source has a pending bit in the status register, except the dma interrupt sourc- es that have the interrupt pending bits located in the prlr register. these bits are set by hardware when the corre- sponding interrupt event occurs. an interrupt re- quest is performed only if the related mask bits are set in the imr register and the jblpd has priority. the pending bits have to be reset by the user soft- ware. note that until the pending bits are set (while the corresponding mask bits are set), the jblpd processes interrupt requests. so, if at the end of an interrupt routine the related pending bit is not reset, another interrupt request is performed. to reset the pending bits, different actions have to be done, depending on each bit: see the descrip- tion of the status and prlr registers. priority level interrupt source higher error, tla eodm, eofm rdrf, reob lower trdy, teob interrupt vector interrupt source v[7:3] 000b error, tla v[7:3] 010b eodm, eofm v[7:3] 100b rdrf, reob v[7:3] 110b trdy, teob 9
297/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.6 dma features the jblpd can use the st9 on-chip direct mem- ory access (dma) channels to provide high-speed data transactions between the jblpd and contig- uous locations of register file and memory. the transactions can occur from and toward the jblpd. the maximum number of transactions that each dma channel can perform is 222 with regis- ter file or 65536 with memory. control of the dma features is performed using registers located in the jblpd register page (ivr, prlr, imr, rdapr, rdcpr, tdapr, tdcpr). the priority level of the dma features of the jblpd with respect to the other st9 peripherals and the cpu is the same as programmed in the prlr register for the interrupt sources. in the in- ternal priority level order of the jblpd, depending on the value of the dmasusp bit in the options register, the dma may or may not have a higher priority than the interrupt sources. refer to the interrupt and dma chapters of the da- tasheet for details on priority levels. the dma features are enabled by setting the ap- propriate enabling bits (rxd_m, txd_m) in the imr register. it is also possible to select the direc- tion of the dma transactions. once the dma table is completed (the transaction counter reaches 0 value), an interrupt request to the cpu is generated if the related mask bit is set (rdrf_m bit in reception, trdy_m bit in trans- mission). this kind of interrupt is called end of block. the peripheral sends two different end of block interrupts depending on the direction of the dma (receiving end of block (reob) - transmit- ting end of block (teob)). these interrupt sourc- es have dedicated interrupt pending bits in the prlr register (reobp, teobp) and they are mapped to the same interrupt vectors: receive data register full (rdrf) and transmit ready (trdy) respectively. the same correspondence exists for the internal priority between interrupts and interrupt vectors. 10.9.6.1 dma between jblpd and register file if the dma transaction is made between the jblpd and the register file, one register is re- quired to hold the dma address and one to hold the dma transaction counter. these two registers must be located in the register file: the dma ad- dress register in an even addressed register, the dma transaction counter in the following register (odd address). they are pointed to by the dma transaction counter pointer register (rdcpr register in receiving, tdcpr register in transmit- ting) located in the jblpd register page. to select dma transactions with the register file, the control bits rdcpr.rf/mem in receiving mode or tdcpr.rf/mem in transmitting mode must be set. the transaction counter register must be initial- ized with the number of dma transfers to perform and it will be decremented after each transaction. the dma address register must be initialized with the starting address of the dma table in the regis- ter file, and it is incremented after each transac- tion. these two registers must be located between addresses 00h and dfh of the register file. when the dma occurs between jblpd and reg- ister file, the tdapr register (in transmission) and the rdapr register (in reception) are not used. 10.9.6.2 dma between jblpd and memory space if the dma transaction is made between the jblpd and memory, a register pair is required to hold the dma address and another register pair to hold the dma transaction counter. these two pairs of registers must be located in the register file. the dma address pair is pointed to by the dma address pointer registers (rdapr register in reception, tdapr register in transmission) lo- cated in the jblpd register page; the dma trans- action counter pair is pointed to by the dma transaction counter pointer registers (rdcpr register in reception, tdcpr register in transmis- sion) located in the jblpd register page. to select dma transactions with memory space, the control bits rdcpr.rf/mem in receiving mode or tdcpr.rf/mem in transmitting mode must be reset. the transaction counter register pair must be ini- tialized with the number of dma transfers to per- form and it will be decremented after each transac- tion. the dma address register pair must be ini- tialized with the starting address of the dma table in memory space, and it is incremented after each transaction. these two register pairs must be lo- cated between addresses 00h and dfh of the register file. 9
298/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.6.3 dma management in reception mode the dma in reception is performed when the rdrf bit of the status register is set (by hard- ware). the rdrf bit is reset as soon as the dma cycle is finished. to enable the dma feature, the rxd_m bit of the imr register must be set (by software). each dma request performs the transfer of a sin- gle byte from the rxdata register of the peripher- al toward register file or memory space ( figure 134 ). each dma transfer consists of three operations that are performed with minimum use of cpu time: C a load from the jblpd data register (rxdata) to a location of register file/memory addressed through the dma address register (or register pair); C a post-increment of the dma address register (or register pair); C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. note : when the reobp pending bit is set (at the end of the last dma transfer), the reception dma enable bit (rxd_m) is automatically reset by hard- ware. however, the dma can be disabled by soft- ware resetting the rxd_m bit. note : the dma request acknowledge could de- pend on the priority level stored in the prlr regis- ter. figure 134. dma in reception mode jblpd peripheral rxdata register file or memory space data received previous data current address pointer 9
299/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.6.4 dma management in transmission mode dma in transmission is performed when the trdy bit of the status register is set (by hardware). the trdy bit is reset as soon as the dma cycle is finished. to enable the dma feature, the txd_m bit in the imr register must be set (by software). compared to reception, in transmission each dma request performs the transfer of either a single byte or a couple of bytes depending on the value of the transmit opcode bits (txop.op[2:0]) writ- ten during the dma transfer. the table of values managed by the dma must be a sequence of opcode bytes (that will be written in the txop register by the dma) each one followed by a data byte (that will be written in the txdata register by the dma) if the opcode needs it (see figure 135 ). each dma cycle consists of the following transfers for a total of three/six operations that are per- formed with minimum use of cpu time: C a load to the jblpd transmit opcode register (txop) from a location of register file/memory addressed through the dma address register (or register pair); C a post-increment of the dma address register (or register pair); C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed; and if the transmit opcode placed in txop re- quires a datum: C a load to the peripheral data register (txdata) from a location of register file/memory ad- dressed through the dma address register (or register pair); it is the next location in the tx- data transfer cycle; C a post-increment of the dma address register (or register pair); C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. note : when the teobp pending bit is set (at the end of the last dma transfer), the transmission dma enable bit (txd_m) is automatically reset by hardware. however, the dma can be disabled by software resetting the txd_m bit. note: when using dma, the txop byte is written before the txdata register. this order is accept- ed by the jblpd only when the dma in transmis- sion is enabled. note : the dma request acknowledge could de- pend on the priority level stored in the prlr regis- ter. in the same way, some time can occur be- tween the transfer of the first byte and the transfer of the second one if another interrupt or dma re- quest with higher priority occurs. 10.9.6.5 dma suspend mode in the jblpd it is possible to suspend or not to suspend the dma transfer while some j1850 pro- tocol events occur. the selection between the two modes is done by programming the dmasusp bit of the options register. if the dmasusp bit is set (dma suspended mode), while the error or tla flag is set, the dma transfers are suspended, to allow the user program to handle the event condition. if the dmasusp bit is reset (dma not suspended mode), the previous flags have no effect on the dma transfers. 9
300/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) figure 135. dma in transmission mode jblpd peripheral txdata register file or memory space opcode sent txop previous opcode sent data sent 1st byte 2nd byte (data required) previous data sent (data required) opcode (data not required) opcode (data required) previous opcode sent (data not required) data 9
301/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.7 register description the jblpd peripheral uses 48 registers that are mapped in a single page of the st9 register file. twelve registers are mapped from r240 (f0h) to r251 (fbh): these registers are usually used to control the jblpd. see section 10.9.7.1 un- stacked registers for a detailed description of these registers. thirty-six registers are mapped from r252 (fch) to r255 (ffh). this is obtained by creating 9 sub- pages, each containing 4 registers, mapped in the same register addresses; 4 bits (rsel[3:0]) of a register (options) are used to select the current sub-page. see section 10.9.7.2 stacked regis- ters section for a detailed description of these reg- isters. the st9 register file page used is 23 (17h). note : bits marked as reserved should be left at their reset value to guarantee software compatibil- ity with future versions of the jblpd. figure 136. jblpd register map status clksel r240 (f0h) r241 (f1h) r242 (f2h) r243 (f3h) r244 (f4h) r245 (f5h) r246 (f6h) r247 (f7h) r248 (f8h) r249 (f9h) r250 (fah) r251 (fbh) r252 (fch) r253 (fdh) r254 (feh) r255 (ffh) txdata rxdata txop control paddr error ivr prlr imr options creg0 creg1 creg2 creg3 rdapr rdcpr tdapr tdcpr freg0 freg31 freg30 freg29 freg28 freg1 freg2 freg3 freg4 freg5 freg6 freg7 freg10 freg11 freg9 freg8 freg12 freg13 freg15 freg14 freg16 freg17 freg18 freg19 freg20 freg21 freg22 freg23 freg24 freg25 freg26 freg27 9
302/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.7.1 un-stacked registers status register (status) r240 - read/write register page: 23 reset value: 0100 0000 (40h) the bits of this register indicate the status of the jblpd peripheral. this register is forced to its reset value after the mcu reset and while the control.jdis bit is set. while the control.je bit is reset, all bits ex- cept idle are forced to their reset values. bit 7 = err error flag. the err bit indicates that one or more bits in the error register have been set. as long as any bit in the error register remains set, the err bit re- mains set. when all the bits in the error register are cleared, then the err bit is reset by hardware. the err bit is also cleared on reset or while the control.je bit is reset, or while the con- trol.jdis bit is set. if the err_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: no error 1: one or more errors have occurred bit 6 = trdy transmit ready flag. the trdy bit indicates that the txop register is ready to accept another opcode for transmission. the trdy bit is set when the txop register is empty and it is cleared whenever the txop regis- ter is written (by software or by dma). trdy will be set again when the transmit state machine ac- cepts the opcode for transmission. when attempting to transmit a data byte without using dma, two writes are required: first a write to txdata, then a write to the txop. C if a byte is written into the txop which results in tra getting set, then the trdy bit will immedi- ately be set. C if a tla occurs and the opcode for which trdy is low is scheduled for this frame, then trdy will go high, if the opcode is scheduled for the next frame, then trdy will stay low. C if an ibd, ifd or crce error condition occurs, then trdy will be set and any queued transmit opcode scheduled to transmit in the present frame will be cancelled by the jblpd peripher- al. a msgx opcode scheduled to be sent in the next frame will not be cancelled for these errors, so trdy would not get set. C an rbrk error condition cancels all transmits for this frame or any successive frames, so the trdy bit will always be immediately set on an rbrk condition. trdy is set on reset or while control.je is re- set, or while the control.jdis bit is set. if the trdy_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: txop register not ready to receive a new op- code 1: txop register ready to receive a new opcode bit 5 = rdrf receive data register full flag. rdrf is set when a complete data byte has been received and transferred from the serial shift regis- ter to the rxdata register. rdrf is cleared when the rxdata register is read (by software or by dma). rdrf is also cleared on reset or while control.je is reset, or while control.jdis bit is set. if the rdrf_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: rxdata register doesnt contain a new data 1: rxdata register contains a new data bit 4 = tla transmitter lost arbitration. the tla bit gets set when the transmitter loses ar- bitration while transmitting messages or type 1 and 3 ifrs. lost arbitration for a type 2 ifr does not set the tla bit. (type 2 messages require re- tries of the physical address if the arbitration is lost until the frame length is reached (if nfl=0)). the tla bit gets set when, while transmitting a msg, msg+crc, ifr1, ifr3, or ifr3+crc, the decod- ed vpwi data bit symbol received does not match the vpwo data bit symbol that the jblpd is at- tempting to send out. if arbitration is lost, the vpwo line is switched to its passive state and nothing further is transmitted until an end-of-data (eod) symbol is detected on the vpwi line. also, any queued transmit opcode scheduled for trans- mission during this frame is cancelled (but the tra bit is not set). the tla bit can be cleared by software writing a logic zero in the tla position. tla is also cleared on reset or while control.je is reset, or while control.jdis bit is set. if the tla_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: the jblpd doesnt lose arbitration 1: the jblpd loses arbitration 70 err trdy rdrf tla rdt eodm eofm idle 9
303/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 3 = rdt receive data type. the rdt bit indicates the type of data which is in the rxdata register: message byte or ifr byte. any byte received after an sof but before an eodm is considered a message byte type. any byte received after an sof, eodm and nbx is an ifr type. rdt gets set or cleared at the same time that rdrf gets set. rdt is cleared on reset or while control.je is reset, or while control.jdis bit is set. 0: last rxdata byte was a message type byte 1: last rxdata byte was a irf type byte bit 2 = eodm end of data minimum flag. the eodm flag is set when the jblpd decoded vpwi pin has been in a passive state for longer that the minimum tv3 symbol time unless the eodm is inhibited by a sleep, filter or crce, ibd, ifd or rbrk error condition during a frame. eodm bit does not get set when in the sleep mode or when a message is filtered. the eodm bit can be cleared by software writing a logic zero in the eodm position. eodm is cleared on reset, while control.je is reset or while control.jdis bit is set. if the eodm_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: no eod symbol detected 1: eod symbol detected note : the eodm bit is not an error flag. it means that the minimum time related to the passive tv3 symbol is passed. bit 1 = eofm end of frame minimum flag. the eofm flag is set when the jblpd decoded vpwi pin has been in a passive state for longer that the minimum tv4 symbol time. eofm will still get set at the end of filtered frames or frames where sleep mode was invoked. consequently, multiple eofm flags may be encountered be- tween frames of interest. the eofm bit can be cleared by software writing a logic zero in the eofm position. eofm is cleared on reset, while control.je is reset or while control.jdis bit is set. if the eofm_m bit of the imr register is set, when this bit is set an interrupt request occurs. 0: no eof symbol detected 1: eof symbol detected note : the eofm bit is not an error flag. it means that the minimum time related to the passive tv4 symbol is passed. bit 0 = idle idle bus flag idle is set when the jblpd decoded vpwi pin recognized an ifs symbol. that is, an idle bus is when the bus has been in a passive state for long- er that the tv6 symbol time. the idle flag will re- main set as long as the decoded vpwi pin is pas- sive. idle is cleared when the decoded vpwi pin transitions to an active state. note that if the vpwi pin remains in a passive state after je is set, then the idle bit may go high sometime before a tv6 symbol is timed on vpwi (since vpwi timers may be active when je is clear). idle is cleared on reset or while the con- trol.jdis bit is set. 0: j1850 bus not in idle state 1: j1850 bus in idle state jblpd transmit data register (txdata) r241- read/write register page: 23 reset value: xxxx xxxx (xxh) the txdata register is an eight bits read/write register in which the data to be transmitted must be placed. a write to txdata merely enters a byte into the register. to initiate an attempt to transmit the data, the txop register must also be written. when the txop write occurs, the trdy flag is cleared. while the trdy bit is clear, the data is still in the txdata register, so writes to the txdata register with trdy clear will overwrite existing txdata. when the txdata is trans- ferred to the shift register, the trdy bit is set again. reads of the txdata register will always return the last byte written. txdata contents are undefined after a reset. note : the correct sequence to transmit is to write first the txdata register (if datum is needed) and then the txop one. only using the dma, the correct sequence of writ- ing operations is first the txop register and then the txdata one (if needed). 70 txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 9
304/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) jblpd receive data register (rxdata) r242- read only register page: 23 reset value: xxxx xxxx (xxh) the rxdata register is an 8-bit read only register in which the data received from vpwi is stored. vpwi data is transferred from the input vpw de- coder to a serial shift register unless it is inhibited by sleep mode, filter mode or an error condition (ibd, ifd, crce, rbrk) during a frame. when the shift register is full, this data is transferred to the rxdata register, and the rdrf flag gets set. all received data bytes are transferred to rxdata including crc bytes. a read of the rxdata reg- ister will clear the rdrf flag. note that care must be taken when reading rxda- ta subsequent to an rdrf flag. multiple reads of rxdata after an rdrf should only be attempted if the user can be sure that another rdrf will not occur by the time the read takes place. rxdata content is undefined after a reset. jblpd transmit opcode register (txop) r243 - read/write register page: 23 reset value: 0000 0000 (00h) txop is an 8-bit read/write register which contains the instructions required by the jblpd to transmit a byte. a write to the txop triggers the state ma- chine to initialize an attempt to serially transmit a byte out on the vpwo pin. an opcode which trig- gers a message byte or ifr type 3 to be sent will transfer the txdata register contents to the transmit serial shift register. an opcode which trig- gers a message byte or ifr type 3 to be sent with a crc appended will transfer the txdata regis- ter contents to the transmit serial shift register and subsequently the computed crc byte. an opcode which triggers an ifr type 1 or 2 to be sent will transfer the paddr register contents to the trans- mit serial shift register. if a txop opcode is written which is invalid for the bus conditions at the time (e.g. 12 byte frame or ifr3ing an ifr2), then no transmit attempt is tried and the tra bit in the er- ror register is set. transmission of a string of data bytes requires multiple txdata/txop write sequences. each write combination should be accomplished while the trdy flag is set. however, writes to the txop when trdy is not set will be accepted by the state machine, but it may override the previous data and opcode. under normal message transmission conditions the msg opcode is written. if the last data byte of a string is to be sent, then the msg+crc opcode will be written. an ifrx opcode is written if a re- sponse byte or bytes to a received message (i.e. bytes received in rxdata with rdt=0) is wanted to transmit. the message length count bits (mlc[3:0]) may be used to require that the ifr be enabled only if the correct number of message bytes has been received. note : the correct sequence to transmit is to write first the txdata register and then the txop one. only using the dma, the correct sequence of writ- ing operations is first the txop register and then the txdata one (if needed). 70 rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 70 mlc3 mlc2 mlc1 mlc0 - op2 op1 op0 9
305/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 7:4 = mlc[3:0] message length count. message length count bits 3 to 0 are written when the program writes one of the ifr opcodes. upon detection of the eod symbol which delineates the body of a frame from the ifr portion of the frame, the received byte counter is compared against the count contained in mlc[3:0]. if they match, then the ifr will be transmitted. if they do not match, then the tra bit in the error register is set and no transmit attempt occurs. C while nfl=0, an mcl[3:0] decimal value be- tween 1 and 11 is considered valid. mcl[3:0] values of 12, 13, 14, 15 are considered invalid and will set the transmit request aborted (tra) bit in the error register. C while nfl=1, an mcl[3:0] value between 1 and 15 is considered valid. C for nfl=1 or 0, mcl[3:0] bits are dont care dur- ing a msg or msg+crc opcode write. C if writing an ifr opcode and mcl[3:0]=0000, then the message length count check is ignored (i.e. mlc=count is disabled), and the ifr is en- abled only on a correct crc and a valid eod symbol assuming no other error conditions (ifd, ibd, rbrk) appear. bit 3 = reserved . bit 2:0 = op[2:0] transmit opcode select bits. the bits op[2:0] form the code that the transmitter uses to perform a transmit sequence. the codes are listed in table 58 . table 58. opcode definitions msg , message byte opcode. the message byte opcode is set when the user program wants to initiate or continue transmitting the body of a message out the vpwo pin. the body of a message is the string of data bytes following an sof symbol, but before the first eod symbol in a frame. if the j1850 bus is in an idle condition when the opcode is written, an sof symbol is transmitted out the vpwo pin immedi- ately before it transmits the data contained in tx- data. if the jblpd is not in idle and the j1850 transmitter has not been locked out by loss of arbi- tration, then the txdata byte is transferred to the serial output shift register for transmission immedi- ately on completion of any previously transmitted data. the final byte of a message string is not transmitted using the msg opcode (use the msg+crc opcode). special conditions for msg transmit: C 1) a msg cannot be queued on top of an execut- ing ifr3 opcode. if so, then tra is set, and tduf will get set because the transmit state machine will be expecting more data, then the inverted crc is appended to this frame. also, no message byte will be sent on the next frame. C 2) if nfl = 0 and an msg queued without crc on received byte count for this frame=10 will trigger the tra to get set, and tduf will get set because the state machine will be expecting more data and the transmit machine will send the inverted crc after the byte which is pres- ently transmitting. also, no message byte will be sent on the next frame. caution should be taken when tra gets set in these cases because the tduf error sequence may engage before the user program has a chance to rewrite the txop register with the cor- rect opcode. if a tduf error occurs, a subsequent msg write to the txop register will be used as the first byte of the next frame. op[2:0] transmit opcode abbreviation 000 no operation or cancel cancel 001 send break symbol sbrk 010 message byte msg 011 message byte then ap- pend crc msg+crc 100 in-frame response type 1 ifr1 101 in-frame response type 2 ifr2 110 in-frame response type 3 ifr3 111 ifr type 3 then append crc ifr3+crc 9
306/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) msg+crc , message byte then append crc op- code. the message byte with crc opcode is set when the user program wants to transmit a single byte message followed by a crc byte, or transmit the final byte of a message string followed by a crc byte. a single byte message is basically an sof symbol followed by a single data byte retrieved from tx- data register followed by the computed crc byte followed by an eod symbol. if the j1850 bus is in idle condition when the opcode is written, an sof symbol is immediately transmitted out the vpwo pin. it then transmits the byte contained in the txdata register, then the computed crc byte is transmitted. vpwo is then set to a passive state. if the j1850 bus is not idle and the j1850 transmitter has not been locked out by loss of arbi- tration, then the txdata byte is transferred to the serial output shift register for transmission immedi- ately on completion of any previously transmitted data. after completion of the txdata byte the computed crc byte is transferred out the vpwo pin and then the vpwo pin is set passive to time an eod symbol. special conditions for msg+crc transmit: C 1) a msg+crc opcode cannot be queued on top of an executing ifr3 opcode. if so, then tra is set, and tduf will get set because the transmit state machine will be expecting more data, then the inverted crc is appended to this frame. also, no message byte will be sent on the next frame. C 2) if nfl=0, a msg+crc can only be queued if received byte count for this frame <=10 other- wise the tra will get set, and tduf will get set because the state machine will be expecting more data, so the transmit machine will send the inverted crc after the byte which is pres- ently transmitting. also, no message byte will be sent on the next frame. caution should be taken when tra gets set in these cases because the tduf error sequence may engage before the user program has a chance to rewrite the txop register with the cor- rect opcode. if a tduf error occurs, a subsequent msg+crc write to the txop register will be used as the first byte of the next frame. ifr1 , in-frame response type 1 opcode. the in-frame response type 1 (ifr 1) opcode is written if the user program wants to transmit a physical address byte (contained in the paddr register) in response to a message that is currently being received. the user program decides to set up an ifr1 upon receiving a certain portion of the data byte string of an incoming message. no write of the txdata register is required. the ifr1 gets its data byte from the paddr register. the jblpd block will enable the transmission of the ifr1 on these conditions: C 1) the crc check is valid (otherwise the crce is set) C 2) the received message length is valid if ena- bled (otherwise the tra is set) C 3) a valid eod minimum symbol is received (oth- erwise the ifd may eventually get set due to byte synchronization errors) C 4) if nfl = 0 & received byte count for this frame <=11 (otherwise tra is set) C 5) if not presently executing an msg, ifr3, op- code (otherwise tra is set, and tduf will get set because the transmit state machine will be expecting more data, so the inverted crc will be appended to this frame) C 6) if not presently executing an ifr1, ifr2, or ifr3+crc opcode otherwise tra is set (but no tduf) C 7) if not presently receiving an ifr portion of a frame, otherwise tra is set. the ifr1 byte is then attempted according to the procedure described in section transmitting a type 1 ifr. note that if an ifr1 opcode is written, a queued msg or msg+crc is overridden by the ifr1. 9
307/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) ifr2 , in-frame response type 2 opcode. the in-frame response type 2 (ifr2) opcode is set if the user program wants to transmit a physical address byte (contained in the paddr register) in response to a message that is currently being re- ceived. the user program decides to set up an ifr2 upon receiving a certain portion of the data byte string of an incoming message. no write of the txdata register is required. the ifr gets its data byte from the paddr register. the jblpd block will enable the transmission of the ifr2 on these conditions: C 1) the crc check is valid (otherwise the crce is set) C 2) the received message length is valid if ena- bled (otherwise the tra is set) C 3) a valid eod minimum symbol is received (oth- erwise the ifd may eventually get set due to byte synchronization errors) C 4) if nfl = 0 & received byte count for this frame <=11 (otherwise tra is set) C 5) if not presently executing an msg, ifr3, op- code (otherwise tra is set, and tduf will get set because the transmit state machine will be expecting more data, so the inverted crc will be appended to this frame) C 6) if not presently executing an ifr1, ifr2, or ifr3+crc opcodes, otherwise tra is set (but no tduf) C 7) if not presently receiving an ifr portion of a frame, otherwise tra is set. the ifr byte is then attempted according to the procedure described in section transmitting a type 2 ifr. note that if an ifr opcode is written, a queued msg or msg+crc is overridden by the ifr2. ifr3 , in-frame response type 3 opcode. the in-frame response type 3 (ifr3) opcode is set if the user program wants to initiate to transmit or continue to transmit a string of data bytes in re- sponse to a message that is currently being re- ceived. the ifr3 uses the contents of the txdata regis- ter for data. the user program decides to set up an ifr3 upon receiving a certain portion of the data byte string of an incoming message. a previous write of the txdata register should have oc- curred. the jblpd block will enable the transmission of the first byte of an ifr3 string on these conditions: C 1) the crc check is valid (otherwise the crce is set) C 2) the received message length is valid if ena- bled (otherwise the tra is set) C 3) a valid eod minimum symbol is received (oth- erwise the ifd may eventually get set due to byte synchronization errors) C 4) if nfl = 0 & received byte count for this frame <=9 (otherwise tra is set and inverted crc is transmitted due to tduf) C 5) if not presently executing an msg opcode (otherwise tra is set, and tduf will get set be- cause the transmit state machine will be expect- ing more data and the inverted crc will be appended to this frame) C 6) if not presently executing an ifr1, ifr2, or ifr3+crc opcode, otherwise tra is set (but no tduf) C 7) if not presently receiving an ifr portion of a frame, otherwise tra is set. the ifr3 byte string is then attempted according to the procedure described in section transmit- ting a type 3 ifr. note that if an ifr3 opcode is written, a queued msg or msg+crc is overrid- den by the ifr3. the next byte(s) in the ifr3 data string shall also be written with the ifr3 opcode except for the last byte in the string which shall be written with the ifr3+crc opcode. each ifr3 data byte trans- mission is accomplished with a txdata/txop write sequence. the succeeding ifr3 transmit re- quests will be enabled on conditions 4 and 5 listed above. 9
308/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) ifr3+crc , in-frame response type 3 then ap- pend crc opcode. the in-frame response type 3 then append crc opcode (ifr3+crc) is set if the user program wants to either initiate to transmit a single data byte ifr3 followed by a crc, or transmit the last data byte of an ifr3 string followed by the crc byte in response to a message that is currently be- ing received. the ifr3+crc opcode transmits the contents of the txdata register followed by the computed crc byte. the user program decides to set up an ifr3 upon receiving a certain portion of the data byte string of an incoming message. a previous write of the txdata register should have oc- curred. the j1850 block will enable the transmission of the first byte of an ifr3 string on these conditions: C 1) the crc check is valid (otherwise the crce is set) C 2) the received message length is valid if ena- bled (otherwise the tra is set) C 3) a valid eod minimum symbol is received (oth- erwise the ifd may eventually get set due to byte synchronization errors) C 4) if nfl = 0 & received byte count for this frame <=10 (otherwise tra is set and inverted crc is transmitted) C 5) if not presently executing an msg opcode (otherwise tra is set, and tduf will get set be- cause the transmit state machine will be expect- ing more data and the inverted crc will be appended to this frame) C 6) if not presently executing an ifr1, ifr2 or ifr3+crc opcodes, otherwise tra is set (but no tduf) C 7) if not presently receiving an ifr portion of a frame, otherwise tra is set. the ifr3 byte is attempted according to the pro- cedure described in section transmitting a type 3 ifr. the crc byte is transmitted out on comple- tion of the transmit of the ifr3 byte. if this opcode sets up the last byte in an ifr3 data string, then the txdata register contents shall be transmitted out immediately upon completion of the previous ifr3 data byte followed by the trans- mit of the crc byte. in this case the ifr3+crc is enabled on conditions 4 and 5 listed above. note that if an ifr3+crc opcode is written, a queued msg or msg+crc is overridden by the ifr3+crc. sbrk , send break symbol. the sbrk opcode is written to transmit a nominal break (brk) symbol out the vpwo pin. a break symbol can be initiated at any time. once the sbrk opcode is written a brk symbol of the nom- inal tv5 duration will be transmitted out the vpwo pin immediately. to terminate the transmission of an in-progress break symbol the je bit should be set to a logic zero. an sbrk command is non- maskable, it will override any present transmit op- eration, and it does not wait for the present trans- mit to complete. note that in the 4x mode a sbrk will send a break character for the nominal tv5 time times four (4 x tv5) so that all nodes on the bus will recognize the break. a cancel opcode does not override a sbrk command. cancel , no operation or cancel pending trans- mit. the cancel opcode is used by the user program to tell the j1850 transmitter that a previously queued opcode should not be transmitted. the cancel op- code will set the trdy bit. if the jblpd peripheral is presently not transmitting, the cancel command effectively cancels a pending msgx or ifrx op- code if one was queued, or it does nothing if no opcode was queued. if the jblpd peripheral is presently transmitting, then a queued msgx or ifrx opcode is aborted and the tduf circuit may take affect. 9
309/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) jblpd system frequency selection register (clksel) r244- read/write register page: 23 reset value: 0000 0000 (00h) bit 7 = 4x diagnostic four times mode. this bit is set when the j1850 clock rate is chosen four times faster than the standard requests, to force the break symbol (nominally 300 s long) and the transmitter timeout time (nominally 1 ms) at their nominal durations. when the user want to use a 4 times faster j1850 clock rate, the new prescaler factor should be stored in the freq[5:0] bits and the 4x bit must be set with the same instruction. in the same way, to exit from the mode, freq[5:0] and 4x bits must be placed at the previous value with the same in- struction. 0: diagnostic four times mode disabled 1: diagnostic four times mode enabled note : setting this bit, the prescaler factor is not au- tomatically divided by four. the user must adapt the value stored in freq[5:0] bits by software. note : the customer should take care using this mode when the mcu internal frequency is less than 4mhz. bit 6 = reserved. bit 5:0 = freq[5:0] internal frequency selectors. these 6 bits must be programmed depending on the internal frequency of the device. the formula that must be used is the following one: mcu int. freq.= 1mhz * (freq[5:0] + 1). note : to obtain a correct operation of the periph- eral, the internal frequency of the mcu (intclk) must be an integer multiple of 1mhz and the cor- rect value must be written in the register. so an in- ternal frequency less than 1mhz is not allowed. note: if the mcu internal clock frequency is lower than 1mhz, the peripheral is not able to work cor- rectly. if a frequency lower than 1mhz is used, the user program must disable the peripheral. note: when the clock prescaler factor or the mcu internal frequency is changed, the peripheral could lose the synchronization with the j1850 bus. jblpd control register (control) r245- read/write register page: 23 reset value: 0100 0000 (40h) the control register is an eight bit read/write register which contains jblpd control information. reads of this register return the last written data. bit 7 = je jblpd enable. the jblpd block enable bit (je) enables and dis- ables the transmitter and receiver to the vpwo and vpwi pins respectively. when the jblpd pe- ripheral is disabled the vpwo pin is in its passive state and information coming in the vpwi pin is ig- nored. when the jblpd block is enabled, the transmitter and receiver function normally. note that queued transmits are aborted when je is cleared. je is cleared on reset, by software and setting the jdis bit. 0: the peripheral is disabled 1: the peripheral is enabled note : it is not possible to reset the jdis bit and to set the je bit with the same instruction. the cor- rect sequence is to first reset the jdis bit and then set the je bit with another instruction. 70 4x - freq5 freq4 freq3 freq2 freq1 freq0 70 je jdis nfl jdly4 jdly3 jdly2 jdly1 jdly0 9
310/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 6 = jdis peripheral clock frozen . when this bit is set by software, the peripheral is stopped and the bus is not decoded anymore. a reset of the bit restarts the internal state machines as after a mcu reset. the jdis bit is set on mcu reset. 0: the peripheral clock is running 1: the peripheral clock is stopped note: when the jdis bit is set, the status reg- ister, the error register, the imr register and the teobp and reobp bits of the prlr register are forced into their reset value. note : it is not possible to reset the jdis bit and to set the je bit with the same instruction. the cor- rect sequence is to first reset the jdis bit and then set the je bit with another instruction. bit 5 = nfl no frame length check the nfl bit is used to enable/disable the j1850 requirement of 12 bytes maximum per frame limit. the sae j1 850 standard states that a maximum of 12 bytes (including crcs and ifrs) can be on the j1850 between a start of frame symbol (sof) and an end of frame symbol (eof). if this condi- tion is violated, then the jblpd peripheral gets an invalid frame detect (ifd) and the sleep mode ensues until a valid eofm is detected. if the valid frame check is disabled (nfl=1), then no limits are imposed on the number of data bytes which can be sent or received on the bus between an sof and an eof. the default upon reset is for the frame checking to be enabled. the nfl bit is cleared on reset 0: twelve bytes frame length check enabled 1: twelve bytes frame length check disabled bit 4:0 = jdly[4:0] jblpd transceiver external loop delay selector. these five bits are used to select the nominal ex- ternal loop time delay which normally occurs when the peripheral is connected and transmitting in a j1850 bus system. the external loop delay is de- fined as the time between when the vpwo is set to a certain level to when the vpwi recognizes the corresponding (inverted) edge on its input. refer to transmit opcode queuing section and the sae-j1850 standard for information on how the external loop delay is used in timing transmitted symbols. the allowed values are integer values between 0 s and 31 s. jblpd physical address register (paddr) r246- read/write register page: 23 reset value: xxxx xxxx (xxh) the paddr is an eight bit read/write register which contains the physical address of the jblpd peripheral. during initialization the user program will write the paddr register with its physical ad- dress. the physical address is used during in- frame response types 1 and 2 to acknowledge the receipt of a message. the jblpd peripheral will transmit the contents of the paddr register for type 1 or 2 ifrs as defined by the txop register. this register is undefined on reset. 70 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 9
311/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) jblpd error register (error) r247- read only register page: 23 reset value: 0000 0000 (00h) error is an eight bit read only register indicating error conditions that may arise on the vpwo and vpwi pins. a read of the error register clears all bits (except for tto and possibly the rbrk bit) which were set at the time of the read. the register is cleared after the mcu reset, while the con- trol.je bit is reset, or while the control.jdis bit is set. all error conditions that can be read in the error register need to have redundant error indicator flags because: C with je set, the tduf, rdof, tra, crce, ifd, & ibd bits in the error register can only be cleared by reading the register. C the tto bit can only be cleared by clearing the je bit. C the rbrk bit can only be cleared by reading the error register after the break condition has disappeared. error condition indicator flags associated with the error condition are cleared when the error condi- tion ends. since error conditions may alter the ac- tions of the transmitter and receiver, the error con- dition indicators must remain set throughout the error condition. all error conditions, including the rbrk condition, are events that get set during a particular clock cycle of the prescaled clock of the peripheral. the ifd, ibd, rbrk, and crce error conditions are then cleared when a valid eof symbol is detected from the vpwi pin. the tra error condition is a singular event that sets the cor- responding error register bit, but this error itself causes no other actions. bit 7 = tto transmitter timeout flag the tto bit is set when the vpwo pin has been in a logic one (or active) state for longer than 1 ms. this flag is the output of a diagnostic circuit based on the prescaled system clock input. if the 4x bit is not set, the tto will trip if the vpwo is constantly active for 1000 prescaled clock cycles. if the 4x bit is set, then the tto will timeout at 4000 prescaled clock cycles. when the tto flag is set then the di- agnostic circuit will disable the vpwo signal, and disable the jblpd peripheral. the user program must then clear the je bit to remove the tto error. it can then retry the block by setting the je bit again. the tto bit can be used to determine if the exter- nal j1850 bus is shorted low. since the transmitter looks for proper edges returned at the vpwi pin for its timing, a lack of edges seen at vpwi when trying to transmit (assuming the rbrk does not get set) would indicate a constant low condition. the user program can take appropriate actions to test the j1850 bus circuit when a tto occurs. note that a transmit attempt must occur to detect a bus shorted low condition. the tto bit is cleared while the control.je bit is reset or while the control.jdis bit is set. tto is cleared on reset. 0: vpwo line at 1 for less than 1 ms 1: vpwo line at 1 for longer than 1 ms bit 6 = tduf transmitter data underflow. the tduf will be set to a logic one if the transmit- ter expects more information to be transmitted, but a txop write has not occurred in time (by the end of transmission of the last bit). the transmitter knows to expect more information from the user program when transmitting messag- es or type 3 ifrs only. if an opcode is written to txop that does not include appending a crc byte, then the jblpd peripheral assumes more data is to be written. when the jblpd peripheral has shifted out the data byte it must have the next data byte in time to place it directly next to it. if the user program does not place new data in the tx- data register and write the txop register with a proper opcode, then the crc byte which is being kept tabulated by the transmitter is logically invert- ed and transmitted out the vpwo pin. this will en- sure that listeners will detect this message as an error. in this case the tduf bit is set to a logic one. tduf is cleared by reading the error register with tduf set. tduf is also cleared on reset, while the control.je bit is reset or while the control.jdis bit is set. 0: no transmitter data underflow condition oc- curred 1: transmitter data underflow condition occurred 70 tto tduf rdof tra rbrk crce ifd ibd 9
312/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 5 = rdof receiver data overflow the rdof gets set to a logic one if the data in the rxdata register has not been read and new data is ready to be transferred to the rxdata register. the old rxdata information is lost since it is overwritten with new data. rdof is cleared by reading the error register with rdof set, while the control.je bit is reset or while the control.jdis bit is set, or on reset. 0: no receiver data overflow condition occurred 1: receiver data overflow condition occurred bit 4 = tra transmit request aborted the tra gets set to a logic one if a transmit op- code is aborted by the jblpd state machine. many conditions may cause a tra. they are ex- plained in the transmit opcode section. if the tra bit gets set after a txop write, then a transmit is not attempted, and the trdy bit is not cleared. if a tra error condition occurs, then the requested transmit is aborted, and the jblpd peripheral takes appropriate measures as described under the txop register section. tra is cleared on reset, while the control.je bit is reset or while the control.jdis bit is set. 0: no transmission request aborted 1: transmission request aborted bit 3 = rbrk received break symbol flag the rbrk gets set to a logic one if a valid break (brk) symbol is detected from the filtered vpwi pin. a break received from the j1850 bus will can- cel queued transmits of all types. the rbrk bit re- mains set as long as the break character is detect- ed from the vpwi. reads of the error register will not clear the rbrk bit as long as a break char- acter is being received. once the break character is gone, a final read of the error register clears this bit. an rbrk error occurs once for a frame if it is re- ceived during a frame. afterwards, the receiver is disabled from receiving information (other than the break) until an eofm symbol is received. rbrk bit is cleared on reset, while the con- trol.je bit is reset or while the control.jdis bit is set. the rbrk bit can be used to detect j1850 bus shorted high conditions. if rbrk is read as a logic high multiple times before an eofm occurs, then a possible bus shorted high condition exists. the user program can take appropriate measures to test the bus if this condition occurs. note that this bit does not necessarily clear when error is read. 0: no valid break symbol received 1: valid break symbol received bit 2 = crce cyclic redundancy check error the receiver section always keeps a running tab of the crc of all data bytes received from the vpwl since the last eod symbol. the crc check is per- formed when a valid eod symbol is received both after a message string (subsequent to an sof symbol) and after an ifr3 string (subsequent to an nb0 symbol). if the received crc check fails, then the crce bit is set to a logic one. crc errors are inhibited if the jblpd peripheral is in the sleep or filter and not presently transmitting mode. a crc error occurs once for a frame. after- wards, the receiver is disabled until an eofm symbol is received and queued transmits for the present frame are cancelled (but the tra bit is not set). crce is cleared when error is read. it is also cleared while the control.je bit is reset or while the control.jdis bit is set, or on reset. 0: no crc error detected 1: crc error detected bit 1 = ifd invalid frame detect the ifd bit gets set when the following conditions are detected from the filtered vpwi pin: C an sof symbol is received after an eod mini- mum, but before an eof minimum. C an sof symbol is received when expecting data bits. C if nfl = 0 and a message frame greater than 12 bytes (i.e. 12 bytes plus one bit) has been re- ceived in one frame. C an eod minimum time has elapsed when data bits are expected. C a logic 0 or 1 symbol is received (active for tv1 or tv2) when an sof was expected. C the second eodm symbol received in a frame is not followed directly by an eofm symbol. ifd errors are inhibited if the jblpd peripheral is in the sleep or filter and not presently transmit- ting mode. an ifd error occurs once for a frame. afterwards, the receiver is disabled until an eofm symbol is received, and queued transmits for the present frame are cancelled (but the tra bit is not set). ifd is cleared when error is read. it is also cleared while the control.je bit is reset or while the control.jdis bit is set or on reset. 0: no invalid frame detected 1: invalid frame detected 9
313/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 0 = ibd invalid bit detect. the ibd bit gets set whenever the receiver detects that the filtered vpwi pin was not fixed in a state long enough to reach the minimum valid symbol time of tv1 (or 35 s). any timing event less than 35 s (and, of course, > 7 s since the vpwi digit- al filter will not allow pulses less than this through its filter) is considered as noise and sets the ibd accordingly. at this point the jblpd peripheral will cease transmitting and receiving any information until a valid eof symbol is received. ibd errors are inhibited if the jblpd peripheral is in the sleep or filter and not presently transmit- ting mode. an ibd error occurs once for a frame. afterwards, the receiver is disabled until an eofm symbol is received, and queued transmits for the present frame are cancelled (but the tra bit is not set). ibd is cleared when error is read. note that if an invalid bit is detected during a bus idle condi- tion, the ibd flag gets set and a new eofmin must be seen after the invalid bit before commencing to receive again. ibd is also cleared while the con- trol.je bit is reset or while the control.jdis bit is set and on reset. 0: no invalid bit detected 1: invalid bit detected jblpd interrupt vector register (ivr) r248- read/write (except bits 2:1) register page: 23 reset value: xxxx xxx0 (xxh) bit 7:3 = v[7:3] interrupt vector base address. user programmable interrupt vector bits. bit 2:1 = ev[2:1] encoded interrupt source (read only). ev2 and ev1 are set by hardware according to the interrupt source, given in table 59 (refer to the status register bits description about the explana- tion of the meaning of the interrupt sources) table 59. interrupt sources bit 0 = reserved. jblpd priority level register (prlr) r249- read/write register page: 23 reset value: 0001 0000 (10h) bit 7:5 = prl[2:0] priority level bits the priority with respect to the other peripherals and the cpu is encoded with these three bits. the value of 0 has the highest priority, the value 7 has no priority. after the setting of this priority lev- el, the priorities between the different interrupt sources and dma of the jblpd peripheral is hard- ware defined (refer to the status register bits de- scription, the interrupts management and the section about the explanation of the meaning of the interrupt sources). depending on the value of the op- tions.dmasusp bit, the dma transfers can or cannot be suspended by an error or tla event. refer to the description of dmasusp bit. table 60. internal interrupt and dma priorities without dma suspend mode table 61. internal interrupt and dma priorities with dma suspend mode 70 v7 v6 v5 v4 v3 ev2 ev1 - ev2 ev1 interrupt sources 0 0 error, tla 0 1 eodm, eofm 1 0 rdrf, reob 1 1 trdy, teob 70 prl2 prl1 prl0 slp - - reobp teobp priority level event sources higher priority tx-dma rx-dma error, tla eodm, eofm rdrf, reob lower priority trdy, teob priority level event sources higher priority error, tla tx-dma rx-dma eodm, eofm rdrf, reob lower priority trdy, teob 9
314/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 4 = slp receiver sleep mode. the slp bit is written to one when the user pro- gram does not want to receive any data from the jblpd vpwi pin until an eofm symbol occurs. this mode is usually set when a message is re- ceived that the user does not require - including messages that the jblpd is transmitting. if the jblpd is not transmitting and is in sleep mode, no data is transferred to the rxdata regis- ter, the rdrf flag does not get set, and errors as- sociated with received data (rdof, crce, ifd, ibd) do not get set. also, the eodm flag will not get set. if the jblpd peripheral is transmitting and is in sleep mode, no data is transferred to the rxdata register, the rdrf flag does not get set and the rdof error flag is inhibited. the crce, ifd, and ibd flags, however, will not be inhibited while transmitting in sleep mode. the slp bit cannot be written to zero by the user program. the slp bit is set on reset or tto get- ting set, and it will stay set upon je getting set until an eofm symbol is received. the slp gets cleared on reception of an eof or a break symbol. slp is set while control.je is reset and while control.jdis is set. 0: the jblpd is not in sleep mode 1: the jblpd is in sleep mode bit 3:2 = reserved. bit 1 = reop receiver dma end of block pend- ing . this bit is set after a receiver dma cycle to mark the end of a block of data. an interrupt request is performed if the rdrf_m bit of the imr register is set. reobp should be reset by software in order to avoid undesired interrupt routines, especially in initialisation routine (after reset) and after entering the end of block interrupt routine. writing 0 in this bit will cancel the interrupt re- quest. this bit is reset when the control.jdis bit is set at least for 6 mcu clock cycles (3 nops). note : when the reobp flag is set, the rxd_m bit is reset by hardware. note: reobp can only be written to 0. bit 0 = teop transmitter dma end of block pending . this bit is set after a transmitter dma cycle to mark the end of a block of data. an interrupt request is performed if the trdy_m bit of the imr register is set. teobp should be reset by software in order to avoid undesired interrupt routines, especially in in- itialisation routine (after reset) and after entering the end of block interrupt routine. writing 0 in this bit will cancel the interrupt re- quest. this bit is reset when the control.jdis bit is set at least for 6 mcu clock cycles (3 nops). note : when the teobp flag is set, the txd_m bit is reset by hardware. note: teobp can only be written to 0. jblpd interrupt mask register (imr) r250 - read/write register page: 23 reset value: 0000 0000 (00h) to enable an interrupt source to produce an inter- rupt request, the related mask bit must be set. when these bits are reset, the related interrupt pending bit can not generate an interrupt. note: this register is forced to its reset value if the control.jdis bit is set at least for 6 clock cy- cles (3 nops). if the jdis bit is set for a shorter time, the bits could be reset or not reset. bit 7 = err_m error interrupt mask bit. this bit enables the error interrupt source to gen- erate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: error interrupt source masked 1: error interrupt source un-masked bit 6 = trdy_m transmit ready interrupt mask bit. this bit enables the transmit ready interrupt source to generate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: trdy interrupt source masked 1: trdy interrupt source un-masked 70 err_ m trdy_ m rdrf_ m tla_ m rxd_ m eodm_ m eofm_ m txd_ m 9
315/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 5 = rdrf_m receive data register full inter- rupt mask bit. this bit enables the receive data register full in- terrupt source to generate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: rdrf interrupt source masked 1: rdrf interrupt source un-masked bit 4 = tla_m transmitter lost arbitration inter- rupt mask bit. this bit enables the transmitter lost arbitration in- terrupt source to generate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: tla interrupt source masked 1: tla interrupt source un-masked bit 3 = rxd_m receiver dma mask bit. if this bit is 0 no receiver dma request will be generated, and the rdrf bit, in the status regis- ter (status), can request an interrupt. if rxd_m bit is set to 1 then the rdrf bit can request a dma transfer. rxd_m is reset by hardware when the transaction counter value decrements to zero, that is when a receiver end of block condition oc- curs (reobp flag set). this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: receiver dma disabled 1: receiver dma enabled bit 2 = eodm_m end of data minimum interrupt mask bit. this bit enables the end of data minimum inter- rupt source to generate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: eodm interrupt source mask 1: eodm interrupt source un-masked bit 1 = eofm_m end of frame minimum interrupt mask bit. this bit enables the end of frame minimum inter- rupt source to generate an interrupt request. this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: eofm interrupt source masked 1: eofm interrupt source un-masked bit 0 = txd_m transmitter dma mask bit. if this bit is 0 no transmitter dma request will be generated, and the trdy bit, in the status regis- ter (status), can request an interrupt. if txd_m bit is set to 1 then the trdy bit can request a dma transfer. txd_m is reset by hardware when the transaction counter value decrements to zero, that is when a transmitter end of block condition occurs (teobp flag set). this bit is reset if the control.jdis bit is set at least for 6 clock cycles (3 nops). 0: transmitter dma disabled 1: transmitter dma enabled jblpd options and register groups selection register (options) r251- read/write register page: 23 reset value: 0000 0000 (00h) bit 7 = inpol vpwi input polarity selector. this bit allows the selection of the polarity of the rx signal coming from the transceivers. depend- ing on the specific transceiver, the rx signal is in- verted or not inverted respect the vpwo and the j1850 bus line. 0: vpwi input is inverted by the transceiver with respect to the j1850 line. 1: vpwi input is not inverted by the transceiver with respect to the j1850 line. bit 6 = nbsyms nb symbol form selector. this bit allows the selection of the form of the nor- malization bits (nb0/nb1). 0: nb0 active long symbol (tv2), nb1 active short symbol (tv1) 1: nb0 active short symbol (tv1), nb1 active long symbol (tv2) 70 inpol nbsyms dmasusp loopb rsel3 rsel2 rsel1 rsel0 9
316/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) bit 5 = dmasusp dma suspended selector. if this bit is 0, jblpd dma has higher priority with respect to the interrupts of the peripheral. dma is performed even if an interrupt request is already scheduled or if the relative interrupt rou- tine is in execution. if the bit is 1, while the error or tla flag of the status register are set, the dma transfers are suspended. as soon as the flags are reset, the dma transfers can be performed. 0: dma not suspended 1: dma suspended note: this bit has effect only on the priorities of the jblpd peripheral. bit 4 = loopb local loopback selector. this bit allows the local loopback mode. when this mode is enabled (loopb=1), the vpwo out- put of the peripheral is sent to the vpwi input with- out inversions whereas the vpwo output line of the mcu is placed in the passive state. moreover the vpwi input of the mcu is ignored by the pe- ripheral. (refer to figure 133 ). 0: local loopback disabled 1: local loopback enabled note: when the loopb bit is set, also the inpol bit must be set to obtain the correct management of the polarity. bit 3:0 = rsel[3:0] registers group selection bits. these four bits are used to select one of the 9 groups of registers, each one composed of four registers that are stacked at the addresses from r252 (fch) to r255 (ffh) of this register page (23). unless the wanted registers group is already selected, to address a specific registers group, these bits must be correctly written. this feature allows that 36 registers (4 dma regis- ters - rdadr, rdcpr, tdapr, tdcpr - and 32 message filtering registers - freg[0:31]) are mapped using only 4 registers (here called current registers - creg[3:0]). since the message filtering registers (freg[0:31]) are seldom read or written, it is sug- gested to always reset the rsel[3:0] bits after ac- cessing the freg[0:31] registers. in this way the dma registers are the current registers. 9
317/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) jblpd current register 0 (creg0) r252- read/write register page: 23 reset value: xxxx xxxx (xxh) depending on the rsel[3:0] value of the op- tions register, this register is one of the following stacked registers: rdapr, freg0, freg4, freg8, freg12, freg16, freg20, freg24, freg28. jblpd current register 1 (creg1) r253 - read/write register page: 23 reset value: xxxx xxxx (xxh) depending on the rsel[3:0] value of the op- tions register, this register is one of the following stacked registers: rdcpr, freg1, freg5, freg9, freg13, freg17, freg21, freg25, freg29. jblpd current register 2 (creg2) r254- read/write register page: 23 reset value: xxxx xxxx (xxh) depending on the rsel[3:0] value of the op- tions register, this register is one of the following stacked registers: tdapr, freg2, freg6, freg10, freg14, freg18, freg22, freg26, freg30. jblpd current register 3 (creg3) r255- read/write register page: 23 reset value: xxxx xxxx (xxh) depending on the rsel[3:0] value of the op- tions register, this register is one of the following stacked registers: tdcpr, freg3, freg7, freg11, freg15, freg19, freg23, freg27, freg31. table 62. stacked registers map 70 b7 b6 b5 b4 b3 b2 b1 b0 70 b7 b6 b5 b4 b3 b2 b1 b0 70 b7 b6 b5 b4 b3 b2 b1 b0 70 b7 b6 b5 b4 b3 b2 b1 b0 rsel[3:0] current registers 0000b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b creg0 rdapr freg0 freg4 freg8 freg12 freg16 freg20 freg24 freg28 creg1 rdcpr freg1 freg5 freg9 freg13 freg17 freg21 freg25 freg29 creg2 tdapr freg2 freg6 freg10 freg14 freg18 freg22 freg26 freg30 creg3 tdcpr freg3 freg7 freg11 freg15 freg19 freg23 freg27 freg31 9
318/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) 10.9.7.2 stacked registers see the description of the options register to obtain more information on the map of the regis- ters of this section. jblpd receiver dma address pointer register (rdapr) r252 - rsel[3:0]=0000b register page: 23 reset value: xxxx xxxx (xxh) to select this register, the rsel[3:0] bits of the options register must be reset bit 7:1 = ra[7:1] receiver dma address pointer. rdapr contains the address of the pointer (in the register file) of the receiver dma data source when the dma between the peripheral and the memory space is selected. otherwise, when the dma between the peripheral and register file is selected, this register has no meaning. see section 10.9.6.2 for more details on the use of this register. bit 0 = ps memory segment pointer selector. this bit is set and cleared by software. it is only meaningful if rdcpr.rf/mem = 1. 0: the isr register is used to extend the address of data received by dma (see mmu chapter) 1: the dmasr register is used to extend the ad- dress of data received by dma (see mmu chap- ter) jblpd receiver dma transaction counter register (rdcpr) r253 - rsel[3:0]=0000b register page: 23 reset value: xxxx xxxx (xxh) to select this register, the rsel[3:0] bits of the options register must be reset bit 7:1 = rc[7:1] receiver dma counter pointer. rdcpr contains the address of the pointer (in the register file) of the dma receiver transaction counter when the dma between peripheral and memory space is selected. otherwise, if the dma between peripheral and register file is selected, this register points to a pair of registers that are used as dma address register and dma transac- tion counter. see section 10.9.6.1 and section 10.9.6.2 for more details on the use of this register. bit 0 = rf/mem receiver register file/memory selector. if this bit is set to 1, then the register file will be selected as destination, otherwise the memory space will be used. 0: receiver dma with memory space 1: receiver dma with register file jblpd transmitter dma address point- er register (tdapr) r254 - rsel[3:0]=0000b register page: 23 reset value: xxxx xxxx (xxh) to select this register, the rsel[3:0] bits of the options register must be reset bit 7:1 = ta[7:1] transmitter dma address point- er. tdapr contains the address of the pointer (in the register file) of the transmitter dma data source when the dma between the memory space and the peripheral is selected. otherwise, when the dma between register file and the peripheral is selected, this register has no meaning. see section 10.9.6.2 for more details on the use of this register. bit 0 = ps memory segment pointer selector. this bit is set and cleared by software. it is only meaningful if tdcpr.rf/mem = 1. 0: the isr register is used to extend the address of data transmitted by dma (see mmu chapter) 1: the dmasr register is used to extend the ad- dress of data transmitted by dma (see mmu chapter) 70 ra7ra6ra5ra4ra3ra2ra1 ps 70 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rf/mem 70 ta7 ta6 ta5 ta4 ta3 ta2 ta1 ps 9
319/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) jblpd transmitter dma transaction counter register (tdcpr) r255 - rsel[3:0]=0000b register page: 23 reset value: xxxx xxxx (xxh) to select this register, the rsel[3:0] bits of the options register must be reset bit 7:1 = tc[7:1] transmitter dma counter point- er. rdcpr contains the address of the pointer (in the register file) of the dma transmitter transaction counter when the dma between memory space and peripheral is selected. otherwise, if the dma between register file and peripheral is selected, this register points to a pair of registers that are used as dma address register and dma transac- tion counter. see section 10.9.6.1 and section 10.9.6.2 for more details on the use of this register. bit 0 = rf/mem transmitter register file/memory selector. if this bit is set to 1, then the register file will be selected as destination, otherwise the memory space will be used. 0: transmitter dma with memory space 1: transmitter dma with register file jblpd message filtering registers (freg[0:31]) r252/r253/r254/r255 - rsel[3]=1 register page: 23 reset value: xxxx xxxx (xxh) 70 tc7 tc6 tc5 tc4 tc3 tc2 tc1 rf/mem register 70 freg0 f_07 f_06 f_05 f_04 f_03 f_02 f_01 f_00 freg1 f_0f f_0e f_0d f_0c f_0b f_0a f_09 f_08 freg2 f_17 f_16 f_15 f_14 f_13 f_12 f_11 f_10 freg3 f_1f f_1e f_1d f_1c f_1b f_1a f_19 f_18 freg4 f_27 f_26 f_25 f_24 f_23 f_22 f_21 f_20 freg5 f_2f f_2e f_2d f_2c f_2b f_2a f_29 f_28 freg6 f_37 f_36 f_35 f_34 f_33 f_32 f_31 f_30 freg7 f_3f f_3e f_3d f_3c f_3b f_3a f_39 f_38 freg8 f_47 f_46 f_45 f_44 f_43 f_42 f_41 f_40 freg9 f_4f f_4e f_4d f_4c f_4b f_4a f_49 f_48 freg10 f_57 f_56 f_55 f_54 f_53 f_52 f_51 f_50 freg11 f_5f f_5e f_5d f_5c f_5b f_5a f_59 f_58 freg12 f_67 f_66 f_65 f_64 f_63 f_62 f_61 f_60 freg13 f_6f f_6e f_6d f_6c f_6b f_6a f_69 f_68 freg14 f_77 f_76 f_75 f_74 f_73 f_72 f_71 f_70 freg15 f_7f f_7e f_7d f_7c f_7b f_7a f_79 f_78 freg16 f_87 f_86 f_85 f_84 f_83 f_82 f_81 f_80 freg17 f_8f f_8e f_8d f_8c f_8b f_8a f_89 f_88 freg18 f_97 f_96 f_95 f_94 f_93 f_92 f_91 f_90 freg19 f_9f f_9e f_9d f_9c f_9b f_9a f_99 f_98 freg20 f_a7 f_a6 f_a5 f_a4 f_a3 f_a2 f_a1 f_a0 freg21 f_af f_ae f_ad f_ac f_ab f_aa f_a9 f_a8 freg22 f_b7 f_b6 f_b5 f_b4 f_b3 f_b2 f_b1 f_b0 freg23 f_bf f_be f_bd f_bc f_bb f_ba f_b9 f_b8 freg24 f_c7 f_c6 f_c5 f_c4 f_c3 f_c2 f_c1 f_c0 freg25 f_cf f_ce f_cd f_cc f_cb f_ca f_c9 f_c8 freg26 f_d7 f_d6 f_d5 f_d4 f_d3 f_d2 f_d1 f_d0 freg27 f_df f_de f_dd f_dc f_db f_da f_d9 f_d8 freg28 f_e7 f_e6 f_e5 f_e4 f_e3 f_e2 f_e1 f_e0 freg29 f_ef f_ee f_ed f_ec f_eb f_ea f_e9 f_e8 freg30 f_f7 f_f6 f_f5 f_f4 f_f3 f_f2 f_f1 f_f0 freg31 f_ff f_fe f_fd f_fc f_fb f_fa f_f9 f_f8 9
320/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) these registers are structured in eight groups of four registers. the user can gain access to these registers programming the rsel[2:0] bits of the options register while the rsel[3] bit of the same register must be placed at 1. in this way the user can select the group where the registers that he/she wants to use are placed. see the descrip- tion of options register for the correspondence between registers and the values of rsel[2:0] bits (see table 62 ). from the functional point of view, the freg[0]- freg[31] registers can be seen as an array of 256 bits involved in the j1850 received message filtering system. the first byte received in a frame (following a valid received sof character) is an identifier (i.d.) byte. it is used by the jblpd peripheral as the address of the 256 bits array. if the bit of the array correspondent to the i.d. byte is set, then the byte is transferred to the rxdata register and the rdrf flag is set. also, every other data byte received in this frame is transferred to the rxdata register unless the jblpd peripheral is put into sleep mode setting the slp bit. if the bit of the array correspondent to the i.d. byte is clear, then the transfer of this byte as well as any byte for the balance of this frame is inhibited, and the rdrf bit remains cleared. the bit 0 of the freg[0] register (freg[0].0 - marked as f_00 in the previous table) corre- sponds to the i.d. byte equal to 00h while the bit 7 of the freg[31] register (freg[31].7 - marked as f_ff in the previous table) corresponds to the i.d. byte equal to ffh. note: the freg registers are undefined upon re- set. because of this, it is strongly recommended that the contents of these registers has to be de- fined before je is set for the first time after reset. otherwise, unpredictable results may occur. 9
321/398 j1850 byte level protocol decoder (jblpd) j1850 byte level protocol decoder (contd) register address 7 0 status reset value f0h err 0 trdy 1 rdrf 0 tla 0 rdt 0 eodm 0 eofm 0 idle 0 txdata reset value f1h txd7 x txd6 x txd5 x txd4 x txd3 x txd2 x txd1 x txd0 x rxdata reset value f2h rxd7 x rxd6 x rxd5 x rxd4 x rxd3 x rxd2 x rxd1 x rxd0 x txop reset value f3h mlc3 0 mlc2 0 mlc1 0 mlc0 0 - 0 op2 0 op1 0 op0 0 clksel reset value f4h 4x 0 - 0 freq5 0 freq4 0 freq3 0 freq2 0 freq1 0 freq0 0 control reset value f5h je 0 jdis 1 nfl 0 jdly4 0 jdly3 0 jdly2 0 jdly1 0 jdly0 0 paddr reset value f6h adr7 x adr6 x adr5 x adr4 x adr3 x adr2 x adr1 x adr0 x error reset value f7h tto 0 tduf 0 rdof 0 tra 0 rbrk 0 crce 0 ifd 0 ibd 0 ivr reset value f8h v7 x v6 x v5 x v4 x v3 x ev2 x ev1 x - 0 prlr reset value f9h prl2 0 prl1 0 prl0 0 slp 1 - 0 - 0 reobp 0 teobp 0 imr reset value fah err_m 0 trdy_m 0 rdrf_m 0 tla_m 0 rxd_m 0 eodm_m 0 eofm_m 0 txd_m 0 options reset value fbh inpol 0 nbsyms 0 dmasusp 0 loopb 0 rsel3 0 rsel2 0 rsel1 0 rsel0 0 creg0 reset value fch b7 x b6 x b5 x b4 x b3 x b2 x b1 x b0 x creg1 reset value fdh b7 x b6 x b5 x b4 x b3 x b2 x b1 x b0 x creg2 reset value feh b7 x b6 x b5 x b4 x b3 x b2 x b1 x b0 x creg3 reset value ffh b7 x b6 x b5 x b4 x b3 x b2 x b1 x b0 x 9
322/398 controller area network (bxcan) 10.10 controller area network (bxcan) 10.10.1 introduction this peripheral basic extended can , named bx- can , interfaces the can network. it supports the can protocol version 2.0a and b. it has been de- signed to manage a high number of incoming mes- sages efficiently with a minimum cpu load. it also meets the priority requirements for transmit mes- sages. for safety-critical applications, the can controller provides all hardware functions for supporting the can time triggered communication option. 10.10.2 main features n supports can protocol version 2.0 a, b active n bit rates up to 1mbit/s n supports the time triggered communication option transmission n three transmit mailboxes n configurable transmit priority n time stamp on sof transmission reception n two receive fifos with three stages n eight scalable filter banks n identifier list feature n configurable fifo overrun n time stamp on sof reception time triggered communication option n disable automatic retransmission mode n 16-bit free running timer n configurable timer resolution n time stamp sent in last two data bytes management n maskable interrupts n software-efficient mailbox mapping at a unique address space 10.10.3 general description in todays can applications, the number of nodes in a network is increasing and often several net- works are linked together via gateways. typically the number of messages in the system (and thus to be handled by each node) has significantly in- creased. in addition to the application messages, network management and diagnostic messages have been introduced. C an enhanced filtering mechanism is required to handle each type of message. furthermore, application tasks require more cpu time, therefore real-time constraints caused by message reception have to be reduced. C a receive fifo scheme allows the cpu to be dedicated to application tasks for a long time pe- riod without losing messages. the standard hlp (higher layer protocol) based on standard can drivers requires an efficient in- terface to the can controller. C all mailboxes and registers are organized in 16- byte pages mapped at the same address and se- lected via a page select register. figure 137. can network topology can node 1 can node 2 can node n can can high low can can rx tx can transceiver can controller st9 mcu can bus application 9
323/398 controller area network (bxcan) controller area network (contd) can 2.0b active core the bxcan module handles the transmission and the reception of can messages fully autonomous- ly. standard identifiers (11-bit) and extended iden- tifiers (29-bit) are fully supported by hardware. control, status and configuration registers the application uses these registers to: C configure can parameters, e.g.baud rate C request transmissions C handle receptions C manage interrupts C get diagnostic information tx mailboxes three transmit mailboxes are provided to the soft- ware for setting up messages. the transmission scheduler decides which mailbox has to be trans- mitted first. acceptance filters the bxcan provides eight scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. receive fifo two receive fifos are used by hardware to store the incoming messages. three complete messag- es can be stored in each fifo. the fifos are managed completely by hardware. figure 138. can block diagram mailbox 2 mailbox 1 7 6 5 can 2.0b active core mailbox 0 transmission acceptance filters tx mailboxes master control scheduler master status transmit control transmit status transmit priority receive fifo error status error int. enable tx error counter rx error counter diagnostic bit timing filter mode filter config. page select interrupt enable mailbox 0 1 2 receive fifo 1 4 3 2 1 filter 0 mailbox 0 1 2 receive fifo 0 control/status/configuration 9
324/398 controller area network (bxcan) controller area network (contd) figure 139. bxcan operating modes 10.10.4 operating modes bxcan has three main operating modes: initiali- zation , normal and sleep . after a hardware reset, bxcan is in sleep mode to reduce power con- sumption and an internal pull-up is active on rx1. the software requests bxcan to enter initializa- tion or sleep mode by setting the inrq or sleep bits in the cmcr register. once the mode has been entered, bxcan confirms it by setting the inak or slak bits in the cmsr register and the internal pull-up is disabled. when neither inak nor slak are set, bxcan is in normal mode. before entering normal mode bxcan always has to syn- chronize on the can bus. to synchronize, bx- can waits until the can bus is idle, this means 11 consecutive recessive bits have been monitored on canrx. 10.10.4.1 initialization mode the software initialization can be done while the hardware is in initialization mode. to enter this mode the software sets the inrq bit in the cmcr register and waits until the hardware has con- firmed the request by setting the inak bit in the cmsr register. to leave initialization mode, the software clears the inqr bit. bxcan has left initialization mode once the inak bit has been cleared by hardware. while in initialization mode, all message transfers to and from the can bus are stopped and the sta- tus of the can bus output cantx is recessive (high). entering initialization mode does not change any of the configuration registers. to initialize the can controller, software has to set up the bit timing registers and the filters. if a filter bank is not used, it is recommended to leave it non active (leave the corresponding fact bit cleared). 10.10.4.2 normal mode once the initialization has been done, the software must request the hardware to enter normal mode, to synchronize on the can bus and start reception and transmission. entering normal mode is done by clearing the inrq bit in the cmcr register and waiting until the hardware has confirmed the re- quest by clearing the inak bit in the cmsr regis- ter. afterwards, the bxcan synchronizes with the data transfer on the can bus by waiting for the oc- currence of a sequence of 11 consecutive reces- sive bits ( o bus idle) before it can take part in bus activities and start message transfer. the initialization of the filter values is independent from initialization mode but must be done while the filter is not active (corresponding factx bit cleared). the filter scale and mode configuration must be configured before entering normal mode. sleep sync initialization normal s l e e p s l e e p * i n r q i n r q i n r q reset slak= 1 inak = 0 slak= x inak = x slak= 0 inak = 1 s l e e p s le e p slak= 0 inak = 0 inrq 9
325/398 controller area network (bxcan) controller area network (contd) 10.10.4.3 low power mode (sleep) to reduce power consumption, bxcan has a low power mode called sleep mode. this mode is en- tered on software request by setting the sleep bit in the cmcr register. in this mode, the bxcan clock is stopped. consequently, software can still access the bxcan registers and mailboxes but the bxcan will not update the status bits. example : if software requests entry to initializa- tion mode by setting the inrq bit while bxcan is in sleep mode, it will not be acknowledged by the hardware, inak stays cleared. bxcan can be woken up (exit sleep mode) either by software clearing the sleep bit or on detection of can bus activity. on can bus activity detection, hardware automat- ically performs the wake-up sequence by clearing the sleep bit if the awum bit in the cmcr regis- ter is set. if the awum bit is cleared, software has to clear the sleep bit w hen a wake-up interrupt occurs, in order to exit from sleep mode. note : if the wake-up interrupt is enabled (wkuie bit set in cier register) a wake-up interrupt will be generated on detection of can bus activity, even if the bxcan automatically performs the wake-up sequence. after the sleep bit has been cleared, sleep mode is exited once bxcan has synchronized with the can bus, refer to figure 3. bxcan operating modes . the sleep mode is exited once the slak bit has been cleared by hardware. 10.10.4.4 test mode test mode can be selected by the silm and lbkm bits in the cdgr register. these bits must be con- figured while bxcan is in initialization mode. once test mode has been selected, the inrq bit in the cmcr register must be reset to enter normal mode. 10.10.4.5 silent mode the bxcan can be put in silent mode by setting the silm bit in the cdgr register. in silent mode, the bxcan is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the can bus and it cannot start a transmission. if the bxcan has to send a dominant bit (ack bit, overload flag, active error flag), the bit is rerouted internally so that the can core monitors this dominant bit, although the can bus may remain in recessive state. silent mode can be used to analyze the traffic on a can bus without affecting it by the transmission of dominant bits (acknowledge bits, error frames). figure 140. bxcan in silent mode 10.10.4.6 loop back mode the bxcan can be set in loop back mode by set- ting the lbkm bit in the cdgr register. in loop back mode, the bxcan treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a receive mailbox. bxcan in loop back mode this mode is provided for self-test functions. to be independent of external events, the can core ig- nores acknowledge errors (no dominant bit sam- pled in the acknowledge slot of a data / remote frame) in loop back mode. in this mode, the bx- can performs an internal feedback from its tx output to its rx input. the actual value of the can- rx input pin is disregarded by the bxcan. the transmitted messages can be monitored on the cantx pin. bxcan cantx canrx tx rx =1 bxcan cantx canrx tx rx 9
326/398 controller area network (bxcan) controller area network (contd) 10.10.4.7 loop back combined with silent mode it is also possible to combine loop back mode and silent mode by setting the lbkm and silm bits in the cdgr register. this mode can be used for a hot selftest, meaning the bxcan can be tested like in loop back mode but without affecting a run- ning can system connected to the cantx and canrx pins. in this mode, the canrx pin is dis- connected from the bxcan and the cantx pin is held recessive. figure 141. bxcan in combined mode 10.10.5 functional description 10.10.5.1 transmission handling in order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (dlc) and the data before requesting the transmission by setting the corresponding txrq bit in the mcsr register. once the mailbox has left empty state, the soft- ware no longer has write access to the mailbox registers. immediately after the txrq bit has been set, the mailbox enters pending state and waits to become the highest priority mailbox, see transmit priority . as soon as the mailbox has the highest priority it will be scheduled for transmis- sion. the transmission of the message of the scheduled mailbox will start (enter transmit state) when the can bus becomes idle. once the mail- box has been successfully transmitted, it will be- come empty again. the hardware indicates a suc- cessful transmission by setting the rqcp and txok bits in the mcsr and ctsr registers. if the transmission fails, the cause is indicated by the alst bit in the mcsr register in case of an ar- bitration lost, and/or the terr bit, in case of transmission error detection. transmit priority by identifier: when more than one transmit mailbox is pending, the transmission order is given by the identifier of the message stored in the mailbox. the message with the lowest identifier value has the highest pri- ority according to the arbitration of the can proto- col. if the identifier values are equal, the lower mailbox number will be scheduled first. by transmit request order: the transmit mailboxes can be configured as a transmit fifo by setting the txfp bit in the cmcr register. in this mode the priority order is given by the transmit request order. this mode is very useful for segmented transmis- sion. abort a transmission request can be aborted by the user setting the abrq bit in the mcsr register. in pending or scheduled state, the mailbox is abort- ed immediately. an abort request while the mail- box is in transmit state can have two results. if the mailbox is transmitted successfully the mailbox becomes empty with the txok bit set in the mcsr and ctsr registers. if the transmission fails, the mailbox becomes scheduled, the trans- mission is aborted and becomes empty with txok cleared. in all cases the mailbox will be- come empty again at least at the end of the cur- rent transmission. non-automatic retransmission mode this mode has been implemented in order to fulfil the requirement of the time triggered communi- cation option of the can standard. to configure the hardware in this mode the nart bit in the cmcr register must be set. in this mode, each transmission is started only once. if the first attempt fails, due to an arbitration loss or an error, the hardware will not automatical- ly restart the message transmission. at the end of the first transmission attempt, the hardware considers the request as completed and sets the rqcp bit in the mcsr register. the result of the transmission is indicated in the mcsr regis- ter by the txok, alst and terr bits. bxcan cantx canrx tx rx =1 9
327/398 controller area network (bxcan) controller area network (contd) figure 142. transmit mailbox states empty txrq=1 rqcp=x txok=x pending rqcp=0 txok=0 scheduled rqcp=0 txok=0 mailbox has transmit rqcp=0 txok=0 can bus = idle transmit failed * nart transmit succeeded mailbox does not empty rqcp=1 txok=0 highest priority have highest priority empty rqcp=1 txok=1 abrq=1 abrq=1 transmit failed * nart tme = 1 tme = 0 tme = 0 tme = 0 tme = 1 tme = 1 9
328/398 controller area network (bxcan) controller area network (contd) 10.10.5.2 time triggered communication mode in this mode, the internal counter of the can hard- ware is activated and used to generate the time stamp value stored in the mtsrh and mtsrl registers. the internal counter is captured on the sample point of the start of frame bit in both re- ception and transmission. 10.10.5.3 reception handling for the reception of can messages, three mailboxes organized as a fifo are provided. in order to save cpu load, simplify the software and guarantee data consistency, the fifo is managed completely by hardware. the application accesses the messages stored in the fifo through the fifo output mailbox. valid message a received message is considered as valid when it has been received correctly according to the can protocol (no error until the last but one bit of the eof field) and it passed through the identifier fil- tering successfully, see section 0.1.5.4 identifier filtering . 9
329/398 controller area network (bxcan) figure 143. receive fifo states empty valid message fmp=0x00 fovr=0 pending_1 fmp=0x01 fovr=0 received pending_2 fmp=0x10 fovr=0 pending_3 fmp=0x11 fovr=0 valid message received release overrun fmp=0x11 fovr=1 mailbox release mailbox valid message received valid message received release mailbox release mailbox valid message received rfom=1 rfom=1 rfom=1 9
330/398 controller area network (bxcan) controller area network (contd) fifo management starting from the empty state, the first valid mes- sage received is stored in the fifo which be- comes pending_1 . the hardware signals the event setting the fmp[1:0] bits in the crfr regis- ter to the value 01b. the message is available in the fifo output mailbox. the software reads out the mailbox content and releases it by setting the rfom bit in the crfr register. the fifo be- comes empty again. if a new valid message has been received in the meantime, the fifo stays in pending_1 state and the new message is availa- ble in the output mailbox. if the application does not release the mailbox, the next valid message will be stored in the fifo which enters pending_2 state (fmp[1:0] = 10b). the storage process is repeated for the next valid message putting the fifo into pending_3 state (fmp[1:0] = 11b). at this point, the software must release the output mailbox by setting the rfom bit, so that a mailbox is free to store the next valid message. otherwise the next valid message re- ceived will cause a loss of message. refer also to section 0.1.5.5 message storage overrun once the fifo is in pending_3 state (i.e. the three mailboxes are full) the next valid message recep- tion will lead to an overrun and a message will be lost. the hardware signals the overrun condition by setting the fovr bit in the crfr register. which message is lost depends on the configura- tion of the fifo: C if the fifo lock function is disabled (rflm bit in the cmcr register cleared) the last message stored in the fifo will be overwritten by the new incoming message. in this case the latest mes- sages will be always available to the application. C if the fifo lock function is enabled (rflm bit in the cmcr register set) the most recent message will be discarded and the software will have the three oldest messages in the fifo available. reception related interrupts once a message has been stored in the fifo, the fmp[1:0] bits are updated and an interrupt request is generated if the fmpie bit in the cier register is set. when the fifo becomes full (i.e. a third message is stored) the full bit in the crfr register is set and an interrupt is generated if the ffie bit in the cier register is set. on overrun condition, the fovr bit is set and an interrupt is generated if the fovie bit in the cier register is set. 10.10.5.4 identifier filtering in the can protocol the identifier of a message is not associated with the address of a node but re- lated to the content of the message. consequently a transmitter broadcasts its message to all receiv- ers. on message reception a receiver node de- cides - depending on the identifier value - whether the software needs the message or not. if the mes- sage is needed, it is copied into the ram. if not, the message must be discarded without interven- tion by the software. to fulfil this requirement, the bxcan controller provides eight configurable and scalable filter- banks (0-7) to the application, in order to receive only the messages the software needs. this hard- ware filtering saves cpu resources which would be otherwise needed to perform filtering by soft- ware. each filter bank consists of eight 8-bit regis- ters, cfxr[0:7]. scalable width to optimize and adapt the filters to the application needs, each filter bank can be scaled independ- ently. depending on the filter scale a filter bank provides: C one 32-bit filter for the stdid[10:0], ide, ex- tid[17:0] and rtr bits. C two 16-bit filters for the stdid[10:0], rtr and ide bits. C four 8-bit filters for the stdid[10:3] bits. the other bits are considered as dont care. C one 16-bit filter and two 8-bit filters for filtering the same set of bits as the 16 and 8-bit filters de- scribed above. refer to figure 8 . furthermore, the filters can be configured in mask mode or in identifier list mode. mask mode in mask mode the identifier registers are associat- ed with mask registers specifying which bits of the identifier are handled as must match or as dont care. identifier list mode in identifier list mode, the mask registers are used as identifier registers. thus instead of defin- ing an identifier and a mask, two identifiers are specified, doubling the number of single identifi- ers. all bits of the incoming identifier must match the bits specified in the filter registers. 9
331/398 controller area network (bxcan) controller area network (contd) figure 144. filter bank scale configuration - register organisation one 32-bit filter two 16-bit filters one 16-bit / two 8-bit filters four 8-bit filters cfxr0 cfxr4 cfxr1 cfxr5 cfxr2 cfxr6 cfxr3 cfxr7 cfxr0 cfxr2 cfxr1 cfxr3 cfxr4 cfxr6 cfxr5 cfxr7 cfxr0 cfxr2 cfxr1 cfxr3 cfxr4 cfxr5 cfxr6 cfxr7 cfxr0 cfxr1 cfxr2 cfxr3 cfxr4 cfxr5 cfxr6 cfxr7 x = filter bank number fscx = 3 fscx = 2 fscx = 1 fscx = 0 filter bank scale configuration 1 these bits are located in the cfcr register filter bank scale config. bits 1 identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. stid10:3 stid2:0 rtr ide exid17:15 exid14:7 exid6:0 bit mapping stid10:3 bit mapping stid10:3 stid2:0 rtr ide exid17:15 identifier mask/ident. bit mapping 9
332/398 controller area network (bxcan) controller area network (contd) filter bank scale and mode configuration the filter banks are configured by means of the corresponding cfcrx register. to configure a fil- ter bank it must be deactivated by clearing the fact bit in the cfcr register. the filter scale is configured by means of the fsc[1:0] bits in the corresponding cfcr register, refer to figure 8 . the identifier list or identifier mask mode for the corresponding mask/identifier registers is config- ured by means of the fmclx and fmchx bits in the cfmr register. the fmclx bit defines the mode for the two least significant bytes, and the fmchx bit the mode for the two most significant bytes of filter bank x. examples: C if filter bank 1 is configured as two 16-bit filters, then the fmcl1 bit defines the mode of the cf1r2 and cf1r3 registers and the fmch1 bit defines the mode of the cf1r6 and cf1r7 reg- isters. C if filter bank 2 is configured as four 8-bit filters, then the fmcl2 bit defines the mode of the cf2r1 and cf2r3 registers and the fmch2 bit defines the mode of the cf2r5 and cf2r7 reg- isters. note : in 32-bit configuration, the fmclx and fm- chx bits must have the same value to ensure that the four mask/identifier registers are in the same mode. to filter a group of identifiers, configure the mask/ identifier registers in mask mode. to select single identifiers, configure the mask/ identifier registers in identifier list mode. filters not used by the application should be left deactivated. filter match index once a message has been received in the fifo it is available to the application. typically application data are copied into ram locations. to copy the data to the right location the application has to identify the data by means of the identifier. to avoid this and to ease the access to the ram loca- tions, the can controller provides a filter match index. this index is stored in the mailbox together with the message according to the filter priority rules. thus each received message has its associated filter match index. the filter match index can be used in two ways: C compare the filter match index with a list of ex- pected values. C use the filter match index as an index on an ar- ray to access the data destination location. for non-masked filters, the software no longer has to compare the identifier. if the filter is masked the software reduces the comparison to the masked bits only. filter priority rules depending on the filter combination it may occur that an identifier passes successfully through sev- eral filters. in this case the filter match value stored in the receive mailbox is chosen according to the following rules: C a filter in identifier list mode prevails on an filter in mask mode. C a filter with full identifier coverage prevails over filters covering part of the identifier, e.g. 16-bit fil- ters prevail over 8-bit filters. C filters configured in the same mode and with identical coverage are prioritized by filter number and register number. the lower the number the higher the priority. 9
333/398 controller area network (bxcan) controller area network (contd) figure 145. filtering mechanism - example the example above shows the filtering principle of the bxcan. on reception of a message, the iden- tifier is compared first with the filters configured in identifier list mode. if there is a match, the mes- sage is stored in the associated fifo and the in- dex of the matching filter is stored in the filter match index. as shown in the example, the identi- fier matches with identifier #2 thus the message content and mfmi 2 is stored in the fifo. if there is no match, the incoming identifier is then compared with the filters configured in mask mode. if the identifier does not match any of the identifi- ers configured in the filters, the message is dis- carded by hardware without disturbing the soft- ware. identifier list message discarded identifier & mask identifier 0 identifier 1 identifier 2 identifier n identifier n+1 mask identifier n+m mask identifier message received ctrl data identifier #2 match message stored receive fifo no match found n: number of single identifiers to receive m: number of identifier groups to receive n and m values depend on the configuration of the filters 9
334/398 controller area network (bxcan) controller area network (contd) 10.10.5.5 message storage the interface between the software and the hard- ware for the can messages is implemented by means of mailboxes. a mailbox contains all infor- mation related to a message; identifier, data, con- trol, status and time stamp information. transmit mailbox the software sets up the message to be transmit- ted in an empty transmit mailbox. the status of the transmission is indicated by hardware in the mcsr register. transmit mailbox mapping receive mailbox when a message has been received, it is available to the software in the fifo output mailbox. once the software has handled the message (e.g. read it) the software must release the fifo output mail- box by means of the rfom bit in the crfr regis- ter to make the next incoming message available. the filter match index is stored in the mfmi regis- ter. the 16-bit time stamp value is stored in the mtsr[0:1] registers. receive mailbox mapping offset to transmit mailbox base ad- dress (bytes) register name 0mcsr 1 mdlc 2 midr0 3 midr1 4 midr2 5 midr3 6 mdar0 7 mdar1 8 mdar2 9 mdar3 10 mdar4 11 mdar5 12 mdar6 13 mdar7 14 mtsr0 15 mtsr1 offset to receive mailbox base ad- dress (bytes) register name 0 mfmi 1 mdlc 2 midr0 3 midr1 4 midr2 5 midr3 6 mdar0 7 mdar1 8 mdar2 9 mdar3 10 mdar4 11 mdar5 12 mdar6 13 mdar7 14 mtsr0 15 mtsr1 9
335/398 controller area network (bxcan) controller area network (contd) figure 146. . can error state diagram 10.10.5.6 error management the error management as described in the can protocol is handled entirely by hardware using a transmit error counter (tecr register) and a re- ceive error counter (recr register), which get in- cremented or decremented according to the error condition. for detailed information about tec and rec management, please refer to the can stand- ard. both of them may be read by software to deter- mine the stability of the network. furthermore, the can hardware provides detailed information on the current error status in cesr register. by means of ceier register and errie bit in cier register, the software can configure the interrupt generation on error detection in a very flexible way. bus-off recovery the bus-off state is reached when tecr is great- er then 255, this state is indicated by boff bit in cesr register. in bus-off state, the bxcan is no longer able to transmit and receive messages. depending on the abom bit in the cmcr register bxcan will recover from bus-off (become error active again) either automatically or on software request. but in both cases the bxcan has to wait at least for the recovery sequence specified in the can standard (128 x 11 consecutive recessive bits monitored on canrx). if abom is set, the bxcan will start the recovering sequence automatically after it has entered bus- off state. if abom is cleared, the software must initiate the recovering sequence by requesting bxcan to en- ter and to leave initialization mode. note : in initialization mode, bxcan does not mon- itor the canrx signal, therefore it cannot com- plete the recovery sequence. to recover, bxcan must be in normal mode . error passive when tec or rec > 127 when tec and rec < 128, error active bus off when tec > 255 when 128 * 11 recessive bits occur: 9
336/398 controller area network (bxcan) controller area network (contd) 10.10.5.7 bit timing the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on the following edges. its operation may be explained simply by splitting nominal bit time into three segments as follows: C synchronization segment (sync_seg) : a bit change is expected to occur within this time seg- ment. it has a fixed length of one time quantum (1 x t can ). C bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can st andard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. C bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. the resynchronization jump width (rjw) defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid- ed the controller itself does not send a recessive bit. if a valid edge is detected in bs1 instead of sync_seg, bs1 is extended by up to rjw so that the sample point is delayed. conversely, if a valid edge is detected in bs2 in- stead of sync_seg, bs2 is shortened by up to rjw so that the transmit point is moved earlier. as a safeguard against programming errors, the configuration of the bit timing register (btr) is only possible while the device is in standby mode. note: for a detailed description of the can bit tim- ing and resynchronization mechanism, please re- fer to the iso 11898 standard. figure 147. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t can t bs1 t bs2 sample point transmit point nominalbittime 1 t bs 1 t bs 2 1 t can ++ ----------------------------------------------------------- - = with: t bs1 = t can x (ts1[3:0] + 1) , t bs2 = t can x (ts2[2:0] + 1), t can = t cpu x brp, t cpu = time period of the cpu clock, brp = brp[5:0] + 1 = baud rate prescaler brp[5:0] is defined in the cbtr0 register, ts1[3:0] and ts2[2:0] are defined in the cbtr1 register. b audrate 1 nominalbittime ------------------------------------------------- = 9
337/398 controller area network (bxcan) controller area network (contd) figure 148. can frames data frame or remote frame data field 8 * n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame (standard identifier) 44 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame notes: ? 0 <= n <= 8 ? sof = start of frame ? id = identifier ? rtr = remote transmission request ? ide = identifier extension bit ? r0 = reserved bit ? dlc = data length code ? crc = cyclic redundancy code ? error flag: 6 dominant bits if node is error active else 6 recessive bits. ? suspend transmission: applies to error passive nodes only. ? eof = end of frame ? ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame rtr ide r0 eof data field 8 * n ctrl field 6 12 crc field 16 ack field 7 sof id dlc crc data frame (extended identifier) 64 + 8 * n ack 2 inter-frame space or overload frame inter-frame space srr ide eof rtr r1 r0 std arbitr. field 20 ext arbitr. field 9
338/398 controller area network (bxcan) controller area network (contd) 10.10.6 interrupts four interrupt vectors are dedicated to bxcan. each interrupt source can be independently ena- bled or disabled by means of the can interrupt enable register (cier) and can error interrupt enable register (ceier). figure 149. event flags and interrupt generation rqcp rqcp fmp mcsr + tmeie cier transmit & fmpie full & ffie fovr & fovie & + crfr1 fifo 1 ewgf ewgie epvf epvie boff bofie lecief lecie & & & & cesr + & errie interrupt interrupt fmp & fmpie full & ffie fovr & fovie + crfr0 fifo 0 interrupt rqcp wkui & wkuie cmsr txmb 0 txmb 1 txmb 2 + interrupt error status change 9
339/398 controller area network (bxcan) controller area network (contd) C the transmit interrupt can be generated by the following events: C transmit mailbox 0 becomes empty, rqcp0 bit in the ctsr register set. C transmit mailbox 1 becomes empty, rqcp1 bit in the ctsr register set. C transmit mailbox 2 becomes empty, rqcp2 bit in the ctsr register set. C the fifo 0 interrupt can be generated by the following events: C reception of a new message, fmp bits in the crfr0 register incremented. C fifo0 full condition, full bit in the crfr0 register set. C fifo0 overrun condition, fovr bit in the crfr0 register set. C the fifo 1 interrupt can be generated by the following events: C reception of a new message, fmp bits in the crfr1 register incremented. C fifo1 full condition, full bit in the crfr1 register set. C fifo1 overrun condition, fovr bit in the crfr1 register set. C the error and status change interrupt can be generated by the following events: C error condition, for more details on error con- ditions please refer to the can error status register (cesr). C wake-up condition, sof monitored on the can rx signal. 10.10.7 register access protection erroneous access to certain configuration regis- ters can cause the hardware to temporarily disturb the whole can network. therefore the following registers can be modified by software only while the hardware is in initialization mode: cbtr0, cbtr1, cfcr0, cfcr1, cfmr and cdgr registers. although the transmission of incorrect data will not cause problems at the can network level, it can severely disturb the application. a transmit mail- box can be only modified by software while it is in empty state, refer to figure 6. transmit mailbox states the filters must be deactivated before their value can be modified by software. the modification of the filter configuration (scale or mode) can be done by software only in initialization mode. 9
340/398 controller area network (bxcan) controller area network (contd) 10.10.8 register description 10.10.8.1 control and status registers can master control register (cmcr) reset value: 0000 0010 (02h) bit 7 = ttcm time triggered communication mode - read/set/clear 0: time triggered communication mode disabled. 1: time triggered communication mode enabled note: for more information on time triggered communication mode, please refer to section 0.1.5.2 time triggered communication mode . bit 6 = abom automatic bus-off management - read/set/clear this bit controls the behaviour of the can hard- ware on leaving the bus-off state. 0: the bus-off state is left on software request, once 128 x 11 recessive bits have been moni- tored and the software has first set and cleared the inrq bit of the cmcr register. 1: the bus-off state is left automatically by hard- ware once 128 x 11 recessive bits have been monitored. for detailed information on the bus-off state please refer to section 0.1.5.6 error management . bit 5 = awum automatic wake-up mode - read/set/clear this bit controls the behaviour of the can hard- ware on message reception during sleep mode. 0: the sleep mode is left on software request by clearing the sleep bit of the cmcr register. 1: the sleep mode is left automatically by hard- ware on can message detection. the sleep bit of the cmcr register and the slak bit of the cmsr register are cleared by hardware. bit 4 = nart no automatic retransmission - read/set/clear 0: the can hardware will automatically retransmit the message until it has been successfully transmitted according to the can standard. 1: a message will be transmitted only once, inde- pendently of the transmission result (successful, error or arbitration lost). bit 3 = rflm receive fifo locked mode - read/set/clear 0: receive fifo not locked on overrun. once a re- ceive fifo is full the next incoming message will overwrite the previous one. 1: receive fifo locked against overrun. once a receive fifo is full the next incoming message will be discarded. bit 2 = txfp transmit fifo priority - read/set/clear this bit controls the transmission order when sev- eral mailboxes are pending at the same time. 0: priority driven by the identifier of the message 1: priority driven by the request order (chronologi- cally) bit 1 = sleep sleep mode request - read/set/clear this bit is set by software to request the can hard- ware to enter the sleep mode. sleep mode will be entered as soon as the current can activity (trans- mission or reception of a can frame) has been completed. this bit is cleared by software to exit sleep mode. this bit is cleared by hardware when the awum bit is set and a sof bit is detected on the can rx signal. bit 0 = inrq initialization request - read/set/clear the software clears this bit to switch the hardware into normal mode. once 11 consecutive recessive bits have been monitored on the rx signal the can hardware is synchronized and ready for transmission and reception. hardware signals this event by clearing the inak bit if the cmsr regis- ter. software sets this bit to request the can hardware to enter initialization mode. once software has set the inrq bit, the can hardware waits until the current can activity (transmission or reception) is completed before entering the initialization mode. hardware signals this event by setting the inak bit in the cmsr register. 70 ttcm abom awum nart rflm txfp sleep inrq 9
341/398 controller area network (bxcan) controller area network (contd) can master status register (cmsr) reset value: 0000 0010 (02h) note : to clear a bit of this register the software must write this bit with a one. bit 7:4 = reserved. forced to 0 by hardware. bit 5 = rx receive - read the can hardware is currently receiver. bit 4 = tx transmit - read the can hardware is currently transmitter. bit 3 = wkui wake-up interrupt - read/clear this bit is set by hardware to signal that a sof bit has been detected while the can hardware was in sleep mode. setting this bit generates a status change interrupt if the wkuie bit in the cier reg- ister is set. this bit is cleared by software. bit 2 = erri error interrupt - read/clear this bit is set by hardware when a bit of the cesr has been set on error detection and the corre- sponding interrupt in the ceier is enabled. set- ting this bit generates a status change interrupt if the errie bit in the cier register is set. this bit is cleared by software. bit 1 = slak sleep acknowledge - read this bit is set by hardware and indicates to the software that the can hardware is now in sleep mode. this bit acknowledges the sleep mode re- quest from the software (set sl eep bit in cmcr register). this bit is cleared by hardware when the can hardware has left sleep mode. sleep mode is left when the sleep bit in the cmcr register is cleared. please refer to the awum bit of the cmcr register description for detailed information for clearing sleep bit. bit 0 = inak initialization acknowledge - read this bit is set by hardware and indicates to the software that the can hardware is now in initiali- zation mode. this bit acknowledges the initializa- tion request from the software (set inrq bit in cmcr register). this bit is cleared by hardware when the can hardware has left the initialization mode and is now synchronized on the can bus. to be syn- chronized the hardware has to monitor a se- quence of 11 consecutive recessive bits on the can rx signal. can transmit status register (ctsr) read / write reset value: 0000 0000 (00h) note : to clear a bit of this register the software must write this bit with a one. bit 7 = reserved. forced to 0 by hardware. bit 6 = txok2 transmission ok for mailbox 2 - read this bit is set by hardware when the transmission request on mailbox 2 has been completed suc- cessfully. please refer to figure 6 . this bit is cleared by hardware when mailbox 2 is requested for transmission or when the software clears the rqcp2 bit. bit 5 = txok1 transmission ok for mailbox 1 - read this bit is set by hardware when the transmission request on mailbox 1 has been completed suc- cessfully. please refer to figure 6 . this bit is cleared by hardware when mailbox 1 is requested for transmission or when the software clears the rqcp1 bit. 70 0 0 rx tx wkui erri slak inak 70 0 txok2 txok1 txok0 0 rqcp2 rqcp1 rqcp0 9
342/398 controller area network (bxcan) controller area network (contd) bit 4 = txok0 transmission ok for mailbox 0 - read this bit is set by hardware when the transmission request on mailbox 0 has been completed suc- cessfully. please refer to figure 6 . this bit is cleared by hardware when mailbox 0 is requested for transmission or when the software clears the rqcp0 bit. bit 3 = reserved. forced to 0 by hardware. bit 2 = rqcp2 request completed for mailbox 2 - read/clear this bit is set by hardware to signal that the last re- quest for mailbox 2 has been completed. the re- quest could be a transmit or an abort request. this bit is cleared by software. bit 1 = rqcp1 request completed for mailbox 1 - read/clear this bit is set by hardware to signal that the last re- quest for mailbox 1 has been completed. the re- quest could be a transmit or an abort request. this bit is cleared by software. bit 0 = rqcp0 request completed for mailbox 0 - read/clear this bit is set by hardware to signal that the last re- quest for mailbox 0 has been completed. the re- quest could be a transmit or an abort request. this bit is cleared by software. can transmit priority register (ctpr) all bits of this register are read only. reset value: 0000 0000 (00h) bit 7 = low2 lowest priority flag for mailbox 2 - read this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. bit 6 = low1 lowest priority flag for mailbox 1 - read this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. bit 5 = low0 lowest priority flag for mailbox 0 - read this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority. note : these bits are set to zero when only one mailbox is pending. bit 4 = tme2 transmit mailbox 2 empty - read this bit is set by hardware when no transmit re- quest is pending for mailbox 2. bit 3 = tme1 transmit mailbox 1 empty - read this bit is set by hardware when no transmit re- quest is pending for mailbox 1. bit 2 = tme0 transmit mailbox 0 empty - read this bit is set by hardware when no transmit re- quest is pending for mailbox 0. bit 1:0 = code[1:0] mailbox code - read in case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. in case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority. 70 low2 low1 low0 tme2 tme1 tme0 code1 code0 9
343/398 controller area network (bxcan) controller area network (contd) can receive fifo registers (crfrx) read / write reset value: 0000 0000 (00h) note : to clear a bit in this register, software must write a 1 to the bit. bit 7:6 = reserved. forced to 0 by hardware. bit 5 = rfom release fifo output mailbox - read/set set by software to release the output mailbox of the fifo. the output mailbox can only be released when at least one message is pending in the fifo. setting this bit when the fifo is empty has no ef- fect. if at least two messages are pending in the fifo, the software has to release the output mail- box to access the next message. cleared by hardware when the output mailbox has been released. bit 4 = fovr fifo overrun - read/clear this bit is set by hardware when a new message has been received and passed the filter while the fifo was full. this bit is cleared by software. bit 3 = full fifo full - read/clear set by hardware when three messages are stored in the fifo. this bit is cleared by software. bit 2 = reserved. forced to 0 by hardware. bit 1:0 = fmp[1:0] fifo message pending - read these bits indicate how many messages are pending in the receive fifo. fmp is increased each time the hardware stores a new message in to the fifo. fmp is decreased each time the software releases the output mail- box by setting the rfom bit. can interrupt enable register (cier) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) bit 7 = wkuie wake-up interrupt enable 0: no interrupt when wkui is set. 1: interrupt generated when wkui bit is set. bit 6 = fovie1 fifo overrun interrupt enable 0: no interrupt when fovr is set. 1: interrupt generation when fovr is set. bit 5 = ffie1 fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. bit 4 = fmpie1 fifo message pending interrupt enable 0: no interrupt on fmp[1:0] bits transition from 00b to 01b. 1: interrupt generated on fmp[1:0] bits transition from 00b to 01b. bit 3 = fovie0 fifo overrun interrupt enable 0: no interrupt when fovr bit is set. 1: interrupt generated when fovr bit is set. bit 2 = ffie0 fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. bit 1 = fmpie0 fifo message pending interrupt enable 0: no interrupt on fmp[1:0] bits transition from 00b to 01b. 1: interrupt generated on fmp[1:0] bits transition from 00b to 01b. bit 0 = tmeie transmit mailbox empty interrupt enable 0: no interrupt when rqcpx bit is set. 1: interrupt generated when rqcpx bit is set. note: refer to standard interrupts section. 70 0 0 rfom fovr full 0 fmp1 fmp0 70 wkuie fovie1 ffie1 fmpie1 fovie0 ffie0 fmpie0 tmeie 9
344/398 controller area network (bxcan) controller area network (contd) can error status register (cesr) read / write reset value: 0000 0000 (00h) bit 7 = reserved. forced to 0 by hardware. bit 6:4 = lec[2:0] last error code - read/set/clear this field holds a code which indicates the type of the last error detected on the can bus. if a mes- sage has been transferred (reception or transmis- sion) without error, this field will be cleared to 0. the code 7 is unused and may be written by the cpu to check for update table 63. lec error types bit 3 = reserved. forced to 0 by hardware. bit 2 = boff bus-off flag - read this bit is set by hardware when it enters the bus- off state. the bus-off state is entered on tecr overrun, tec greater than 255, refer to section 0.1.5.6 on page 14 . bit 1 = epvf error passive flag - read this bit is set by hardware when the error passive limit has been reached (receive error counter or transmit error counter greater than 127). bit 1 = ewgf error warning flag - read this bit is set by hardware when the warning limit has been reached. receive error counter or transmit error counter greater than 96. can error interrupt enable register (ceier) all bits of this register are set and clear by soft- ware. read/write reset value: 0000 0000 (00h) bit 7 = errie error interrupt enable 0: no interrupt will be generated when an error condition is pending in the cesr. 1: an interrupt will be generation when an error condition is pending in the cesr. bit 6:5 = reserved. forced to 0 by hardware. bit 4 = lecie last error code interrupt enable 0: erri bit will not be set when the error code in lec[2:0] is set by hardware on error detection. 1: erri bit will be set when the error code in lec[2:0] is set by hardware on error detection. bit 3 = reserved. forced to 0 by hardware. bit 2 = bofie bus-off interrupt enable 0: erri bit will not be set when boff is set. 1: erri bit will be set when boff is set. bit 1 = epvie error passive interrupt enable 0: erri bit will not be set when epvf is set. 1: erri bit will be set when epvf is set. bit 0 = ewgie error warning interrupt enable 0: erri bit will not be set when ewgf is set. 1: erri bit will be set when ewgf is set. note: refer to standard interrupts section. 70 0 lec2 lec1 lec0 0 boff epvf ewgf code error type 0 no error 1 stuff error 2 form error 3 acknowledgment error 4 bit recessive error 5 bit dominant error 6 crc error 7 set by software 70 errie 0 0 lecie 0 bofie epvie ewgie 9
345/398 controller area network (bxcan) controller area network (contd) transmit error counter reg. (tecr) read only reset value: 00h tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. receive error counter reg. (recr) page: 00h read only reset value: 00h rec[7:0] is the receive error counter implement- ing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can stand- ard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. can diagnosis register (cdgr) all bits of this register are set and clear by soft- ware. read / write reset value: 0000 0000 (00h) bit 3 = rx can rx signal - read monitors the actual value of the can_rx pin. bit 2 = samp last sample point - read the value of the last sample point. bit 1 = silm silent mode - read/set/clear 0: normal operation 1: silent mode bit 0 = lbkm loop back mode - read/set/clear 0: loop back mode disabled 1: loop back mode enabled 70 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 70 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 70 0000rxsampsilmlbkm 9
346/398 controller area network (bxcan) controller area network (contd) can bit timing register 0 (cbtr0) this register can only be accessed by the software when the can hardware is in configuration mode. read / write reset value: 0000 0000 (00h) bit 7:6 sjw[1:0] resynchronization jump width these bits define the maximum number of time quanta the can hardware is allowed to lengthen or shorten a bit to perform the resynchronization. bit 5:0 brp[5:0] baud rate prescaler these bits define the length of a time quantum. tq = (brp+1)/fsys for more information on bit timing, please refer to section 0.1.5.7 bit timing . can bit timing register 1 (cbtr1) read / write reset value: 0001 0011 (23h) bit 7 = reserved. forced to 0 by hardware. bit 6:4 ts2[2:0] time segment 2 these bits define the number of time quanta in time segment 2. t bs2 = t can x (ts2[2:0] + 1), bit 3:0 ts1[3:0] time segment 1 these bits define the number of time quanta in time segment 1 t bs1 = t can x (ts1[3:0] + 1) .for more information on bit timing, please refer to section 0.1.5.7 bit timing . can filter page select register (cfpsr) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) bit 7:3 = reserved. forced to 0 by hardware. bit 2:0 = fps[2:0] filter page select - read/write this register contains the filter page number avail- able in page 54. table 64. filter page selection 70 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 70 0 ts22 ts21 ts20 ts13 ts12 ts11 ts10 70 00000fps2fps1fps0 fps[2:0] filter page selected in page 54 0 acceptance filter 0:1 1 acceptance filter 2:3 2 acceptance filter 4:5 3 acceptance filter 6:7 4 filter configuration 5 filter configuration 6 filter configuration 7 filter configuration 9
347/398 controller area network (bxcan) controller area network (contd) 10.10.8.2 mailbox registers this chapter describes the registers of the transmit and receive mailboxes. refer to section 0.1.5.5 message storage for detailed register mapping. transmit and receive mailboxes have the same registers except: C mcsr register in a transmit mailbox is replaced by mfmi register in a receive mailbox. C a receive mailbox is always write protected. C a transmit mailbox is write enable only while empty, corresponding tme bit in the ctpr reg- ister set. mailbox control status register (mcsr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = terr transmission error - read/clear this bit is updated by hardware after each trans- mission attempt. 0: the previous transmission was successful 1: the previous transmission failed due to an error bit 4 = alst arbitration lost - read/clear this bit is updated by hardware after each trans- mission attempt. 0: the previous transmission was successful 1: the previous transmission failed due to an arbi- tration lost bit 3 = txok transmission ok - read/clear the hardware updates this bit after each transmis- sion attempt. 0: the previous transmission failed 1: the previous transmission was successful note : this bit has the same value as the corre- sponding txokx bit in the ctsr register. bit 2 = rqcp request completed - read/clear set by hardware when the last request (transmit or abort) has been performed. cleared by software writing a 1 or by hardware on transmission request. note : this bit has the same value as the corre- sponding rqcpx bit of the ctsr register. clearing this bit clears all the status bits (tx- ok, alst and terr) in the mcsr register and the rqcp and txok bits in the ctsr register. bit 1 = abrq abort request for mailbox - read/set set by software to abort the transmission request for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. setting this bit has no effect when the mailbox is not pending for transmission. bit 0 = txrq transmit mailbox request - read/set set by software to request the transmission for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. note : this register is implemented only in transmit mailboxes. in receive mailboxes, the mfmi regis- ter is mapped at this location. 70 0 0 terr alst txok rqcp abrq txrq 9
348/398 controller area network (bxcan) controller area network (contd) mailbox filter match index (mfmi) this register is read only. reset value: 0000 0000 (00h) bit 7:0 = fmi[7:0] filter match index this register contains the index of the filter the message stored in the mailbox passed through. for more details on identifier filtering please refer to section 0.1.5.4 - filter match index paragraph. note : this register is implemented only in receive mailboxes. in transmit mailboxes, the mcsr reg- ister is mapped at this location. mailbox identifier registers (midr[3:0]) read / write reset value: xxxx xxxx (xxh) midr0 bit 7 = reserved. forced to 0 by hardware. bit 6 = ide extended identifier this bit defines the identifier type of message in the mailbox. 0: standard identifier. 1: extended identifier. bit 5 = rtr remote transmission request 0: data frame 1: remote frame bit 4:0 = stid[10:6] standard identifier 5 most significant bits of the standard part of the identifier. midr1 bit 7:2 = stid[5:0] standard identifier 6 least significant bits of the standard part of the identifier. bit 1:0 = exid[17:16] extended identifier 2 most significant bits of the extended part of the identifier. midr2 bit 7:0 = exid[15:8] extended identifier bit 15 to 8 of the extended part of the identifier. midr3 bit 7:1 = exid[6:0] extended identifier 6 least significant bits of the extended part of the identifier. 70 fmi7 fmi6 fmi5 fmi4 fmi3 fmi2 fmi1 fmi0 70 0 ide rtr stid10 stid9 stid8 stid7 stid6 70 stid5 stid4 stid3 stid2 stid1 stid0 exid17 exid16 70 exid15 exid14 exid13 exid12 exid11 exid10 exid9 exid8 70 exid7 exid6 exid5 exid4 exid3 exid2 exid1 exid0 9
349/398 controller area network (bxcan) controller area network (contd) mailbox data length control regis- ter (mdlc) all bits of this register is write protected when the mailbox is not in empty state. read / write reset value: xxxx xxxx (xxh) bit 7 = tgt transmit global time this bit is active only when the hardware is in the time trigger communication mode, ttcm bit of the ccr register is set. 0: mtsrh and mtsrl registers are not sent. 1: mtsrh and mtsrl registers are sent in the last two data bytes of the message. 6:4 = reserved. forced to 0 by hardware. bit 3:0 = dlc[3:0] data length code this field defines the number of data bytes a data frame contains or a remote frame request. mailbox data registers (mdar[7:0]) all bits of this register are write protected when the mailbox is not in empty state. read / write reset value: xxxx xxxx (xxh) bit 7:0 = data[7:0] data a data byte of the message. a message can con- tain from 0 to 8 data bytes. mailbox time stamp low register (mtslr) read / write reset value: xxxx xxxx (xxh) bit 7:0 = time[7:0] message time stamp low this fields contains the low byte of the 16-bit timer value captured at the sof detection. mailbox time stamp high register (mtshr) read / write reset value: xxxx xxxx (xxh) bit 7:0 = time[15:8] message time stamp high this field contains the high byte of the 16-bit timer value captured at the sof detection. 70 tgt 0 0 0 dlc3 dlc2 dlc1 dlc0 70 data7 data6 data5 data4 data3 data2 data1 data0 70 time7 time6 time5 time4 time3 time2 time1 time0 70 time15 time14 time13 time12 time11 time10 time9 time8 9
350/398 controller area network (bxcan) controller area network (contd) 10.10.8.3 can filter registers can filter configuration reg.0 (cfcr0) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) note : to modify the ffax and fscx bits, the bx- can must be in init mode. bit 7 = ffa1 filter fifo assignment for filter 1 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 6:5 = fsc1[1:0] filter scale configuration these bits define the scale configuration of filter 1. bit 4 = fact1 filter active the software sets this bit to activate filter 1. to modify the filter 1 registers (cf1r[7:0]), the fact1 bit must be cleared. 0: filter 1 is not active 1: filter 1 is active bit 3 = ffa0 filter fifo assignment for filter 0 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 2:1 = fsc0[1:0] filter scale configuration these bits define the scale configuration of filter 0. bit 0 = fact0 filter active the software sets this bit to activate filter 0. to modify the filter 0 registers (cf0r[0:7]), the fact0 bit must be cleared. 0: filter 0 is not active 1: filter 0 is active can filter configuration reg.1 (cfcr1) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) bit 7 = ffa3 filter fifo assignment for filter 3 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 6:5 = fsc3[1:0] filter scale configuration these bits define the scale configuration of filter 3. bit 4 = fact3 filter active the software sets this bit to activate filter 3. to modify the filter 3 registers (cf3r[0:7]) the fact3 bit must be cleared. 0: filter 3 is not active 1: filter 3 is active bit 3 = ffa2 filter fifo assignment for filter 2 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 2:1 = fsc2[1:0] filter scale configuration these bits define the scale configuration of filter 2. bit 0 = fact2 filter active the software sets this bit to activate filter 2. to modify the filter 2 registers (cf2r[0:7]), the fact2 bit must be cleared. 0: filter 2 is not active 1: filter 2 is active 70 ffa1 fsc11 fsc10 fact1 ffa0 fsc01 fsc00 fact0 70 ffa3 fsc31 fsc30 fact3 ffa2 fsc21 fsc20 fact2 9
351/398 controller area network (bxcan) controller area network (contd) can filter configuration reg.2 (cfcr2) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) note : to modify ffax and fscx bits bxcan must be in init mode. bit 7 = ffa5 filter fifo assignment for filter 5 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 6:5 = fsc5[1:0] filter scale configuration these bits define the scale configuration of filter 5. bit 4 = fact5 filter active the software sets this bit to activate filter 5. to modify the filter 5 registers (cf5r[7:0]), the fact5 bit must be cleared. 0: filter 5 is not active 1: filter 5 is active bit 3 = ffa4 filter fifo assignment for filter 4 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 2:1 = fsc4[1:0] filter scale configuration these bits define the scale configuration of filter 4. bit 0 = fact4 filter active the software sets this bit to activate filter 4. to modify the filter 4 registers (cf4r[7:0]), the fact4 bit must be cleared). 0: filter 4 is not active 1: filter 4 is active can filter configuration reg.3 (cfcr3) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) bit 7 = ffa7 filter fifo assignment for filter 7 the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 6:5 = fsc7[1:0] filter scale configuration these bits define the scale configuration of filter 7. bit 4 = fact7 filter active the software sets this bit to activate filter 7. to modify the filter 7 registers (cf7r[7:0]), the fact7 bit must be cleared. 0: filter 7 is not active. 1: filter 7 is active. bit 3 = ffa6 filter fifo assignment for filter 6 this bit allows the software to define whether the message passing through this filter will be as- signed to the receive fifo0 or fifo1. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 bit 2:1 = fsc6[1:0] filter scale configuration these bits define the scale configuration of filter 6. bit 0 = fact6 filter active the software sets this bit to activate filter 6. to modify the filter 6 registers (cf6r[7:0]), the fact6 bit must be cleared. 0: filter 6 is not active 1: filter 6 is active 70 ffa5 fsc51 fsc50 fact5 ffa4 fsc41 fsc40 fact4 70 ffa7 fsc71 fsc70 fact7 ffa6 fsc61 fsc60 fact6 9
352/398 controller area network (bxcan) controller area network (contd) can filter mode reg.1 (cfmr1) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) note : please refer to figure 8. filter bank scale configuration - register organisation bit 7 = fmh7 filter mode high mode of the high registers of filter 7. 0: high registers are in mask mode. 1: high registers are in identifier list mode. bit 6 = fml7 filter mode low mode of the low registers of filter 7. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 5 = fmh6 filter mode high mode of the high registers of filter 6. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 4 = fml6 filter mode low mode of the low registers of filter 6. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 3 = fmh5 filter mode high mode of the high registers of filter 5. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 2 = fml5 filter mode low mode of the low registers of filter 5. 0: low registers are in mask mode 1: low registers are in identifier list mode. bit 1 = fmh4 filter mode high mode of the high registers of filter 4. 0: high registers are in mask mode. 1: high registers are in identifier list mode. bit 0 = fml4 filter mode low mode of the low registers of filter 4. 0: low registers are in mask mode. 1: low registers are in identifier list mode. can filter mode reg.0 (cfmr0) all bits of this register are set and cleared by soft- ware. read / write reset value: 0000 0000 (00h) bit 7 = fmh3 filter mode high mode of the high registers of filter 3. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 6 = fml3 filter mode low mode of the low registers of filter 3. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 5 = fmh2 filter mode high mode of the high registers of filter 2. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 4 = fml2 filter mode low mode of the low registers of filter 2. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 3 = fmh1 filter mode high mode of the high registers of filter 1. 0: high registers are in mask mode 1: high registers are in identifier list mode 70 fmh7 fml7 fmh6 fml6 fmh5 fml5 fmh4 fml4 70 fmh3 fml3 fmh2 fml2 fmh1 fml1 fmh0 fml0 9
353/398 controller area network (bxcan) controller area network (contd) bit 2 = fml1 filter mode low mode of the low registers of filter 1. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 1 = fmh0 filter mode high mode of the high registers of filter 0. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 0 = fml0 filter mode low mode of the low registers of filter 0. 0: low registers are in mask mode 1: low registers are in identifier list mode filter x register[7:0] (cfxr[7:0]) read / write reset value: xxxx xxxx (xxh) in all configurations: bit 7:0 = fb[7:0] filter bits identifier each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: dominant bit is expected 1: recessive bit is expected mask each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: dont care, the bit is not used for the comparison 1: must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. note: each filter x is composed of 8 registers, cfxr[7:0]. depending on the scale and mode configuration of the filter the function of each reg- ister can differ. for the filter mapping, functions description and mask registers association, refer to section 0.1.5.4 identifier filtering . a mask/identifier register in mask mode has the same bit mapping as in identifier list mode. note : to modify these registers, the correspond- ing fact bit in the cfcr register must be cleared. 70 fb7 fb6 fb5 fb4 fb3 fb2 fb1 fb0 9
354/398 controller area network (bxcan) controller area network (contd) 10.10.8.4 page mapping for can 0 / can 1 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 mfmi mdlc mtslr mtshr page 50 / 38 page 51 / 39 page 52 / 40 page 54/0 42/0 page 54/1 42/1 receive fifo 1 tx mailbox 0 tx mailbox 1 acceptance filter 0:1 acceptance filter 2:3 midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 mcsr mdlc mtslr mtshr midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 mcsr mdlc mtslr mtshr midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 page 54/4 42/4 filter configuration cfmr0 cfmr1 reserved reserved cfcr0 cfcr1 cfcr2 cfcr3 reserved reserved reserved reserved reserved reserved reserved reserved cf0r0 cf0r1 cf0r2 cf0r3 cf0r4 cf0r5 cf0r6 cf0r7 cf1r0 cf1r1 cf1r2 cf1r3 cf1r4 cf1r5 cf1r6 cf1r7 cf2r0 cf2r1 cf2r2 cf2r3 cf2r4 cf2r5 cf2r6 cf2r7 cf3r0 cf3r1 cf3r2 cf3r3 cf3r4 cf3r5 cf3r6 cf3r7 cmcr cmsr reserved cfpsr page 48 / 36 control/status ctsr ctpr crfr0 crfr1 cier cesr ceier tec rec cdgr cbtr0 cbtr1 mfmi mdlc mtslr mtshr page 49 / 37 receive fifo 0 midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 page 53 / 41 tx mailbox 2 mcsr mdlc mtslr mtshr midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 page 54/2 42/2 acceptance filter 4:5 cf4r0 cf4r1 cf4r2 cf4r3 cf4r4 cf4r5 cf4r6 cf4r7 cf5r0 cf5r1 cf5r2 cf5r3 cf5r4 cf5r5 cf5r6 cf5r7 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 9
355/398 controller area network (bxcan) controller area network (contd) page mapping for can0 /can1 (contd) page 54/3 42/3 acceptance filter 6:7 cf6r0 cf6r1 cf6r2 cf6r3 cf6r4 cf6r5 cf6r6 cf6r7 cf7r0 cf7r1 cf7r2 cf7r3 cf7r4 cf7r5 cf7r6 cf7r7 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 9
356/398 controller area network (bxcan) controller area network (contd) table 65. bxcan control & status page - register map and reset values address (hex.) register name 765 4 3210 f0h cmcr reset value ttcm 0 abom 0 awum 0 nart 0 rflm 0 txfp 0 sleep 1 inrq 0 f1h cmsr reset value 0 0 rx 0 tx 0 wkui 0 erri 0 slak 0 inak 0 f2h ctsr reset value 0 txok2 0 txok1 0 txok0 00 rqcp2 0 rqcp1 0 rqcp0 0 f3h ctpr reset value low2 0 low1 0 low0 0 tme2 1 tme1 1 tme0 1 code1 0 code0 0 f4h crfr0 reset value 0 0 rfom 0 fovr 0 full 00 fmp1 0 fmp0 0 f5h crfr1 reset value 0 0 rfom 0 fovr 0 full 00 fmp1 0 fmp0 0 f6h cier reset value wkuie 0 fovie1 0 ffie1 0 fmpie1 0 fovie0 0 ffie0 0 fmpie0 0 tmeie 0 f7h cesr reset value 0 lec2 0 lec1 0 lec0 00 boff 0 epvf 0 ewgf 0 f8h ceier reset value errie 0 000 lecie 0 bofie 0 epvie 0 ewgie 0 f9h tecr reset value tec7 0 tec6 0 tec5 0 tec4 0 tec3 0 tec2 0 tec1 0 tec0 0 fah recr reset value rec7 0 rec6 0 rec5 0 rec4 0 rec3 0 rec2 0 rec1 0 rec0 0 fbh cdgr reset value 0 0 0 0 rx 0 samp 0 silm 0 lbkm 0 fch cbtr0 reset value sjw1 0 sjw0 0 brp5 0 brp4 0 brp3 0 brp2 0 brp1 0 brp0 0 fdh cbtr1 reset value 0 ts22 0 ts21 1 ts20 0 ts13 0 ts12 0 ts11 1 ts10 1 feh reserved xxx x xxxx ffh cfpsr reset value 0 0 0 0 0 fps2 0 fps1 0 fps0 0 9
357/398 controller area network (bxcan) controller area network (contd) table 66. bxcan mailbox pages - register map and reset values table 67. bxcan filter configuration page - register map and reset values address (hex.) register name 765 4 3210 f0h receive mfmi reset value fmi7 0 fmi6 0 fmi5 0 fmi4 0 fmi3 0 fmi2 0 fmi1 0 fmi0 0 f0h transmit mcsr reset value 0 0 terr 0 alst 0 txok 0 rqcp 0 abrq 1 txrq 0 f1h mdlc reset value tgt xxxx dlc3 x dlc2 x dlc1 x dlc0 x f2h midr0 reset value x ide x rtr x stid10 x stid9 x stid8 x stid7 x stid6 x f3h midr1 reset value stid5 x stid4 x stid3 x stid2 x stid1 x stid0 x exid17 x exid16 x f4h midr2 reset value exid15 x exid14 x exid13 x exid12 x exid11 x exid10 x exid9 x exid8 x f5h midr3 reset value exid7 x exid6 x exid5 x exid4 x exid3 x exid2 x exid1 x exid0 x f6h:fdh mdar[0:7] reset value mdar7 x mdar6 x mdar5 x mdar4 x mdar3 x mdar2 x mdar1 x mdar0 x feh mtslr reset value time7 x time6 x time5 x time4 x time3 x time2 x time1 x time0 x ffh mtshr reset value time15 x time14 x time13 x time12 x time11 x time10 x time9 x time8 x address (hex.) register name 765 4 3210 f0h cfmr0 reset value fmh3 0 fml3 0 fmh2 0 fml2 0 fmh1 0 fml1 0 fmh0 0 fml0 0 f1h cfmr1 reset value fmh7 0 fml7 0 fmh6 0 fml6 0 fmh5 0 fml5 0 fmh4 0 fml4 0 f2h cfcr0 reset value ffa1 0 fsc11 0 fsc10 0 fact1 0 ffa0 0 fsc01 0 fsc00 0 fact0 0 f3h cfcr1 reset value ffa3 0 fsc31 0 fsc30 0 fact3 0 ffa2 0 fsc21 0 fsc20 0 fact2 0 f4h cfcr2 reset value ffa5 0 fsc51 0 fsc50 0 fact5 0 ffa4 0 fsc41 0 fsc40 0 fact4 0 f5h cfcr3 reset value ffa7 0 fsc71 0 fsc70 0 fact7 0 ffa6 0 fsc61 0 fsc60 0 fact6 0 9
358/398 10-bit analog to digital converter (adc) 10.11 10-bit analog to digital converter (adc) 10.11.1 main characteristics n 10-bit resolution n monotonicity: guaranteed n no missing codes: guaranteed n 3-bit intclk frequency prescaler n internal/external trigger availability n continuous/single modes n autoscan mode n power down mode n 16 10-bit data registers (two per channel) n two analog watchdogs selectable on adjacent channels 10.11.2 introduction the analog to digital converter (adc) consists of an input multiplex channel selector feeding a suc- cessive approximation converter. the conversion time depends on the intclk fre- quency and the prescaler factor stored in the pr[2:0] bits of the clr2 register (r253-page 63)). av dd and av ss are the high and low level refer- ence voltage pins. up to 16 multiplexed analog in- puts are available depending on the specific de- vice type. with the autoscan feature, a group of signals can be converted sequentially by simply programming the starting address of the first ana- log channel to be converted. there are two analog watchdogs used for the continuous hardware monitoring of two consecu- tive input channels selectable by means of the cc[3:0] bits in the clr1 register (r252-page 63). an interrupt request is generated whenever the converted value of either of these two analog in- puts exceeds the upper or lower programmed threshold values. figure 150. adc block diagram interrupt unit int. vector pointer int. control register compare result register threshold h/l register bu threshold h/l register bl threshold h/l register ah threshold h/l register al compare logic data register h/l15 data register h/l14 data register h/l13 data register h/l12 data register h/l11 data register h/l10 data register h/l 9 data register h/l 8 successive analog to digital analog mux ain 15 ain 14 ain 13 ain 12 ain 11 ain 10 ain 9 ain 8 conversion result autoscan logic control reg.2 control logic internal trigger external trigger control reg.1 data register h/l 7 data register h/l 6 data register h/l 5 data register h/l 4 data register h/l 3 data register h/l 2 data register h/l 1 data register h/l 0 ain 7 ain 6 ain 5 ain 4 ain 3 ain 2 ain 1 ain 0 approximation 10 bit analog section ck prescaler ckad intclk (from mft0) (extrg) (clr2) (clr1) converter 9
359/398 10-bit analog to digital converter (adc) analog to digital converter (contd) single and continuous conversion modes are available. these two modes may be triggered by an external signal or, internally, by the multifunc- tion timer mft0. a power-down programmable bit allows the adc to be set in low-power idle mode. the reference voltage av dd can be switched off when the adc is in power down mode. the adc interrupt unit provides two maskable channels (analog watchdog and end of conver- sion) with hardware fixed priority, and up to 7 pro- grammable priority levels. conversion time the maximum ckad frequency allowable for the analog part is 4 mhz. this is provided by a pro- grammable prescaler that divides the st9 system clock (intclk). the user must program the pr[2:0] bits in control logic register 2 (clr2, r253 - page 63) to select the right prescaler divid- ing factor to obtain the correct clock frequency for the analog part. table 69 shows the possible pres- caling values and the related sampling and con- version times. generally, the formulas for the sam- pling and conversion times are: t sample = t intclk x pr[2:0] x 8 t conv = t intclk x pr[2:0] x 28 the user may need to increase the conversion time if a resistor is added to the input pin, for in- stance, as an overvoltage protection. in this case, the adc needs a longer sampling time to work correctly. caution : adc input pin configuration the input analog channel is selected by using the i/o pin alternate function setting (pxc2, pxc1, pxc0 = 1,1,1) as described in the i/o ports sec- tion. the i/o configuration of the port connected to the adc converter is modified in order to prevent the analog voltage present on the i/o pin from causing high power dissipation across the input buffer. analog channels should be maintained in alternate function configuration for this reason. 10.11.3 functional description 10.11.3.1 operating modes two operating modes are available: continuous mode and single mode. to enter one of these modes it is necessary to program the cont bit of the control logic register2 (clr2, r253- page63). the continuous mode is selected when cont is set, while single mode is selected when cont is reset. both modes operate in autoscan configuration, allowing sequential conversion of the input chan- nels. the number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into control reg- ister 1 (sc[3:0] bits). as each conversion is com- pleted, the channel number is automatically incre- mented, up to channel 15. for example, if sc[3:0] are set to 0011, the conversion will proceed from channel 3 to channel 15, whereas, if sc[3:0] are set to 1111, only channel 15 will be converted. when the st bit of control logic register 2 is set, either by software or by hardware (by an internal or external synchronisation trigger signal), the an- alog inputs are sequentially converted (from the first selected channel up to channel 15) and the re- sults are stored in the relevant pair of data regis- ters. in single mode (cont = 0), the st bit is reset by hardware following conversion of channel 15; an end of conversion (ecv) interrupt request is is- sued and the adc waits for a new start event. in continuous mode (cont = 1), a continuous conversion flow is initiated by the start event. when conversion of channel 15 is complete, conversion of channel 's' is initiated (where 's' is specified by the setting of the sc[3:0] bits); this will continue until the st bit is reset by software. in all cases, an ecv interrupt is issued each time channel 15 conversion ends. when channel 'i' is converted ('s' <'i' <15), the re- lated pair of data registers is reloaded with the new conversion result and the previous value is lost. the end of conversion (ecv) interrupt serv- ice routine can be used to save the current values before a new conversion sequence (so as to cre- ate signal sample tables in the register file or in memory). 10.11.3.2 triggering and synchronisation in both modes, conversion may be triggered by in- ternal or external conditions; externally this may be tied to extrg, as an alternate function input on an i/o port pin, and internally, it may be tied to intrg, generated by a multifunction timer pe- ripheral. both external and internal events can be separately masked by programming the extg/ intg bits of the control logic register (clr). the events are internally ored, thus avoiding potential hardware conflicts. however, the correct proce- dure is to enable only one alternate synchronisa- tion condition at any time. 9
360/398 10-bit analog to digital converter (adc) analog to digital converter (contd) the effect of either of these synchronisation modes is to set the st bit by hardware. this bit is reset, in single mode only, at the end of each group of conversions. in continuous mode, all trig- ger pulses after the first are ignored. the synchronisation sources must be at a logic low level for at least the duration of one intclk cycle and, in single mode, the period between trig- ger pulses must be greater than the total time re- quired for a group of conversions. if a trigger oc- curs when the st bit is still set, i.e. when a conver- sion is still in progress, it will be ignored. note: the external trigger will set the clr2.st bit even if the clr2.pow is reset. 10.11.3.3 analog watchdog two internal analog watchdogs are available for highly flexible automatic threshold monitoring of external analog signal levels. depending on the value of the cc[3:0] bits in control logic register1 these two watchdog are mapped onto 2 of the 16 available adjacent channels, allowing the user to set the channel to be monitored. refer to table 68 to see the possible choices for this feature. analog watchdog channels (named as a and b) monitor an acceptable voltage level window for the converted analog inputs. the external voltages applied to inputs a and b are considered normal while they remain below their respective upper thresholds, and above or at their respective lower thresholds. when the external signal voltage level is greater than, or equal to, the upper programmed voltage limit, or when it is less than the lower programmed voltage limit, a maskable interrupt request is gen- erated and the compare results register is up- dated in order to flag the threshold (upper or low- er) and channel (a or b) responsible for the inter- rupt. the four threshold voltages are user pro- grammable in dedicated registers pairs (r244 to r251, page 63). only the 4 msbs of the compare results register are used as flags, each of the four msbs being associated with a threshold con- dition. following a reset, these flags are reset. during normal adc operation, the crr bits are set, in or- der to flag an out of range condition and are auto- matically reset by hardware after a software reset of the analog watchdog request flag in the icr register. 10.11.3.4 power down mode before enabling an adc conversion, the pow bit of the control logic register must be set; this must be done at least 10 m s before the first conver- sion start, in order to correctly bias the analog sec- tion of the converter circuitry. when the adc is not required, the pow bit may be reset in order to reduce the total power con- sumption. this is the reset configuration, and this state is also selected automatically when the st9 is placed in halt mode (following the execution of the halt instruction). figure 151. analog watchdog function figure 152. adc trigger source analog voltage upper threshold lower threshold normal area (window guarded) ext. trigger enable adc trigger int. trigger enable on-chip event software trigger start group of conversions continuous or single mode extrg mft0 9
361/398 10-bit analog to digital converter (adc) analog to digital converter (contd) figure 153. application example: analog watchdog used in motor speed control 10.11.4 interrupts the adc provides two interrupt sources: C end of conversion C analog watchdog request the adc interrupt vector register (ivr, r255 page 63) provides hardware generated flags which indicate the interrupt source, thus allowing the automatic selection of the correct interrupt service routine. the adc interrupt vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the base ad- dress of the four byte area of the interrupt vector table in which the address of the adc interrupt service routines are stored. the analog watchdog interrupt pending bit (awd, icr.6) is automatically set by hardware whenever any of the two guarded analog inputs go out of range. the compare result register (crr) tracks the analog inputs which exceed their programmed thresholds. when two requests occur simultaneously, the an- alog watchdog request has priority over the end of conversion request, which is held pending. the analog watchdog request requires the user to poll the compare result register (crr) to de- termine which of the four thresholds has been ex- ceeded. the threshold status bits are set to flag an out of range condition, and are automatically reset by hardware after a software reset of the analog watchdog request flag in the icr register. the interrupt pending flags, ecv and awd, should be reset by the user within the interrupt service rou- tine. setting either of these two bits by software will cause an interrupt request to be generated. analog watch- dog re- quest 70 lower word address xxxxxx0 0 end of conv. request 70 upper word address xxxxxx1 0 9
362/398 10-bit analog to digital converter (adc) 10.11.5 register description data registers (dihr/dilr) the conversion results for the 16 available chan- nels are loaded into the 32 data registers (two for each channel) following conversion of the corre- sponding analog input. channel 0 data high register (d0hr) r240 - read/write register page: 61 reset value: undefined bits 7:0 = d0.[9:2] : channel 0 9:2 bit data channel 0 data low register (d0lr) r241 - read/write register page: 61 reset value: xx00 0000 bits 7:6 = d0.[1:0] : channel 0 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 1 data high register (d1hr) r242 - read/write register page: 61 reset value: undefined bits 7:0 = d1.[9:2] : channel 1 9:2 bit data channel 1 data low register (d1lr) r243 - read/write register page: 61 reset value: xx00 0000 bits 7:0 = d1.[1:0]: channel 1 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 2 data high register (d2hr) r244 - read/write register page: 61 reset value: undefined bits 7:0 = d2.[9:2] : channel 2 9:2 bit data channel 2 data low register (d2lr) r245 - read/write register page: 61 reset value: xx00 0000 bits 7:0 = d2.[1:0] : channel 2 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 3 data high register (d3hr) r246 - read/write register page: 61 reset value: undefined bits 7:0 = d3.[9:2] : channel 3 9:2 bit data channel 3 data low register (d3lr) r247 - read/write register page: 61 reset value: xx00 0000 bits 7:0 = d3.[1:0] : channel 3 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. 70 d0.9 d0.8 d0.7 d0.6 d0.5 d0.4 d0.3 d0.2 70 d0.1 d0.0 0 0 0 0 0 0 70 d1.9 d1.8 d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 70 d1.1 d1.0 0 0 0 0 0 0 70 d2.9 d2.8 d2.7 d2.6 d2.5 d2.4 d2.3 d2.2 70 d2.1 d2.0 0 0 0 0 0 0 70 d3.9 d3.8 d3.7 d3.6 d3.5 d3.4 d3.3 d3.2 70 d3.1 d3.0 0 0 0 0 0 0 9
363/398 10-bit analog to digital converter (adc) register description (contd) channel 4 data high register (d4hr) r248 - read/write register page: 61 reset value: undefined bits 7:0 = d4.[9:2] : channel 4 9:2 bit data channel 4 data low register (d4lr) r249 - read/write register page: 61 reset value: xx00 0000 bits 7:6 = d4.[1:0] : channel 4 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 5 data high register (d5hr) r250 - read/write register page: 61 reset value: undefined bits 7:0 = d5.[9:2] : channel 5 9:2 bit data channel 5 data low register (d5lr) r251 - read/write register page: 61 reset value: xx00 0000 bits 7:0 = d1.[1:0] : channel 5 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 6 data high register (d6hr) r252 - read/write register page: 61 reset value: undefined bits 7:0 = d6.[9:2] : channel 6 9:2 bit data channel 6 data low register (d6lr) r253 - read/write register page: 61 reset value: xx00 0000 bits 7:0 = d6.[1:0] : channel 6 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 7 data high register (d7hr) r254 - read/write register page: 61 reset value: undefined bits 7:0 = d7.[9:2] : channel 7 9:2 bit data channel 7 data low register (d7lr) r255- read/write register page: 61 reset value: xx00 0000 bits 7:0 = d7.[1:0] : channel 7 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. 70 d4.9 d4.8 d4.7 d4.6 d4.5 d4.4 d4.3 d4.2 70 d4.1 d4.0 0 0 0 0 0 0 70 d5.9 d5.8 d5.7 d5.6 d5.5 d5.4 d5.3 d5.2 70 d5.1 d5.0 0 0 0 0 0 0 70 d6.9 d6.8 d6.7 d6.6 d6.5 d6.4 d6.3 d6.2 70 d6.1 d6.0 0 0 0 0 0 0 70 d7.9 d7.8 d7.7 d7.6 d7.5 d7.4 d7.3 d7.2 70 d7.1 d7.0 0 0 0 0 0 0 9
364/398 10-bit analog to digital converter (adc) register description (contd) channel 8 data high register (d8hr) r240 - read/write register page: 62 reset value: undefined bits 7:0 = d8.[9:2] : channel 8 9:2 bit data channel 8 data low register (d8lr) r241 - read/write register page: 62 reset value: xx00 0000 bits 7:6 = d8.[1:0] : channel 8 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 9 data high register (d9hr) r242 - read/write register page: 62 reset value: undefined bits 7:0 = d9.[9:2] : channel 9 9:2 bit data channel 9 data low register (d9lr) r243 - read/write register page: 62 reset value: xx00 0000 bits 7:0 = d9.[1:0] : channel 9 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 10 data high register (d10hr) r244 - read/write register page: 62 reset value: undefined bits 7:0 = d10.[9:2] : channel 10 9:2 bit data channel 10 data low register (d10lr) r245 - read/write register page: 62 reset value: xx00 0000 bits 7:0 = d10.[1:0] : channel 10 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 11 data high register (d11hr) r246 - read/write register page: 62 reset value: undefined bits 7:0 = d11.[9:2] : channel 11 9:2 bit data channel 11 data low register (d11lr) r247 - read/write register page: 62 reset value: xx00 0000 bits 7:0 = d11.[1:0] : channel 11 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. 70 d8.9 d8.8 d8.7 d8.6 d8.5 d8.4 d8.3 d8.2 70 d8.1 d8.0 0 0 0 0 0 0 70 d9.9 d9.8 d9.7 d9.6 d9.5 d9.4 d9.3 d9.2 70 d9.1 d9.0 0 0 0 0 0 0 70 d10.9 d10.8 d10.7 d10.6 d10.5 d10.4 d10.3 d10.2 70 d10.1 d10.0 0 0 0 0 0 0 70 d11.9 d11.8 d11.7 d11.6 d11.5 d11.4 d11.3 d11.2 70 d11.1 d11.0 0 0 0 0 0 0 9
365/398 10-bit analog to digital converter (adc) register description (contd) channel 12 data high register (d12hr) r248 - read/write register page: 62 reset value: undefined bits 7:0 = d12.[9:2] : channel 12 9:2 bit data channel 12 data low register (d12lr) r249 - read/write register page: 62 reset value: xx00 0000 bits 7:6 = d12.[1:0] : channel 12 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 13 data high register (d13hr) r250 - read/write register page: 62 reset value: undefined bits 7:0 = d13.[9:2] : channel 13 9:2 bit data channel 13 data low register (d13lr) r251 - read/write register page: 62 reset value: xx00 0000 bits 7:0 = d13.[1:0] : channel 13 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 14 data high register (d14hr) r252 - read/write register page: 62 reset value: undefined bits 7:0 = d14.[9:2] : channel 14 9:2 bit data channel 14 data low register (d14lr) r253 - read/write register page: 62 reset value: xx00 0000 bits 7:0 = d14.[1:0] : channel 14 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. channel 15 data high register (d15hr) r254 - read/write register page: 62 reset value: undefined bits 7:0 = d15.[9:2] : channel 15 9:2 bit data channel 15 data low register (d15lr) r255- read/write register page: 62 reset value: xx00 0000 bits 7:0 = d15.[1:0] : channel 15 1:0 bit data bits 5:0 = reserved, forced by hardware to 0. note: if only 8-bit accuracy is required, each data high register can be used to get the conversion result, ignoring the corresponding dxlr register content. 70 d12.9 d12.8 d12.7 d12.6 d12.5 d12.4 d12.3 d12.2 70 d12.1 d12.0 0 0 0 0 0 0 70 d13.9 d13.8 d13.7 d13.6 d13.5 d13.4 d13.3 d13.2 70 d13.1 d13.0 0 0 0 0 0 0 70 d14.9 d14.8 d14.7 d14.6 d14.5 d14.4 d14.3 d14.2 70 d14.1 d14.0 0 0 0 0 0 0 70 d15.9 d15.8 d15.7 d15.6 d15.5 d15.4 d15.3 d15.2 70 d15.1 d15.0 0 0 0 0 0 0 9
366/398 10-bit analog to digital converter (adc) register description (contd) compare result register (crr) r243 - read/write register page: 63 reset value: 0000 xxxx (0xh) two adjacent channels (identified as a and b) can be selected through clr1 register programming (bits cc[3:0]); a level window for the converted an- alog input can be defined on these channels. bits 7 = cbu : compare register ch. b upper threshold set when converted data on channel b is greater than the threshold value set in utbhr/utblr registers. bits 6 = cau : compare register ch. a upper threshold set when converted data on channel a is greater than the threshold value set in utahr/utalr registers. bits 5 = cbl : compare register ch. b lower threshold set when converted data on channel b is less than the threshold value set in ltbhr/ltblr regis- ters. bits 4 = cal: compare register ch. a lower threshold set when converted data on channel a is less than the threshold value set in ltahr/ltalr regis- ters. bits 3:0 = dont care lower threshold registers (ltihr/ ltilr) the two pairs of lower threshold high/low regis- ters are used to store the user programmable low- er threshold 10-bit values, to be compared with the current conversion results, thus setting the lower window limit. channel a lower threshold high register (ltahr) r244 - read register page: 63 reset value: undefined bits 7:0 = lta.[9:2] : channel a [9:2] bit lower threshold channel a lower threshold low register (ltalr) r245 - read/write register page: 63 reset value: xx00 0000 bits 7:6 = lta.[1:0] : channel a [1:0] bit lower threshold bits 5:0 = reserved, forced by hardware to 0. channel b lower threshold high reg- ister (ltbhr) r246 - read/write register page: 63 reset value: undefined bits 7:0 = ltb.[9:2]: channel b [9:2] bit lower threshold 70 cbu cau cbl cal x x x x 70 lta.9 lta.8 lta.7 lta.6 lta.5 lta.4 lta.3 lta.2 70 lta.1 lta.0 0 0 0 0 0 0 70 ltb.7 ltb.7 ltb.5 ltb.4 ltb.3 ltb.2 ltb.1 ltb.0 9
367/398 10-bit analog to digital converter (adc) register description (contd) channel b lower threshold low register (ltblr) r247 - read/write register page: 63 reset value: xx00 0000 bits 7:6 = ltb.[1:0] : channel b [1:0] bit lower threshold bits 5:0 = reserved, forced by hardware to 0. upper threshold registers (utihr/ utilr) the two pairs of upper threshold high/low reg- isters are used to store the user programmable up- per threshold 10-bit values, to be compared with the current conversion results, thus setting the up- per window limit. channel a upper threshold high reg- ister (utar) r248 - read/write register page: 63 reset value: undefined bits 7:0 = uta.[9:2 ]: channel 6 [9:2] bit upper threshold value channel a upper threshold low register (utalr) r249 - read/write register page: 63 reset value: xx00 0000 bits 7:6 = uta.[1:0] : channel a [1:0] bit upper threshold bits 5:0 = reserved, forced by hardware to 0. channel b upper threshold high reg- ister (utbhr) r250 - read/write register page: 63 reset value: undefined bits 7:0 = utb.[9:2] : channel b [9:2] bit upper threshold channel b upper threshold low register (utblr) r251 - read/write register page: 63 reset value: xx00 0000 bits 7:6 = utb.[1:0] : channel b [1:0] bit lower threshold bits 5:0 = reserved, forced by hardware to 0. 70 ltb.1 ltb.0 0 0 0 0 0 0 70 uta.9 uta.8 uta.7 uta.6 uta.5 uta.4 uta.3 uta.2 70 uta.1 uta.0 0 0 0 0 0 0 70 utb.9 utb.8 utb.7 utb.6 utb.5 utb.4 utb.3 utb.2 70 utb.1 utb.0 0 0 0 0 0 0 9
368/398 10-bit analog to digital converter (adc) register description (contd) control logic register 1 (clr1) r252 - read/write register page: 63 reset value: 0000 1111 (0fh) bits 7:4 = sc[3:0] : start conversion channel these four bits define the starting analog input channel (autoscan mode). the first channel ad- dressed by sc[3:0] is converted, then the channel number is incremented for the successive conver- sion, until channel 15 (1111) is converted. when sc3, sc2, sc1 and sc0 are all set, only channel 15 will be converted. bits 3:0 = cc[3:0] : compare channels the programmed value corresponds to the first of the two adjacent channels (a) on which it is possi- ble to define a level window for the converted ana- log input (see table 68 ). note: if a write access to this register occurs, the conversion is re-started from the sc[3:0] channel. control logic register 2 (clr2) r253 - read/write register page: 63 reset value: 1010 0000 (a0h) bits 7:5 = pr[2:0] : intclk frequency prescaler these bits determine the ratio between the adc clock and the system clock (intclk) according to table 69 . 70 sc3 sc2 sc1 sc0 cc3 cc2 cc1 cc0 table 68. compare channels definition cc[3:0] channel a channel b 0000 15 0 0001 0 1 0010 1 2 0011 2 3 0100 3 4 0101 4 5 0110 5 6 0111 6 7 1000 7 8 1001 8 9 1010 9 10 1011 10 11 1100 11 12 1101 12 13 1110 13 14 1111 14 15 70 pr2 pr1 pr0 extg intg pow cont st table 68. compare channels definition cc[3:0] channel a channel b table 69. prescaler programming pr[2:0] t a/d clock / t intcl k conversion /sample time@t intclk= 4mhz conversion /sample time@t intclk= 20mhz 000 1 7 m s/2 m s not allowed 001 2 14 m s/4 m s not allowed 010 3 21 m s/6 m s not allowed 011 4 28 m s/8 m s not allowed 100 5 35 m s/10 m s 7 m s/2 m s 101 6 42 m s/12 m s 8.4 m s/2.4 m s 110 7 49 m s/14 m s 9.8 m s/2.8 m s 111 8 56 m s/16 m s 11.2 m s/3.2 m s 9
369/398 10-bit analog to digital converter (adc) register description (contd) bit 4 = extg : external trigger enable . this bit is set and cleared by software. 0: external trigger disabled. 1: external trigger enabled. allows a conversion sequence to be started on the subsequent edge of the external signal applied to the extrg pin (when enabled as an alternate function). bit 3 = intg : internal trigger enable . this bit is set and cleared by software. 0: internal trigger disabled. 1: internal trigger enabled. allows a conversion se- quence to be started, synchronized by an inter- nal signal (on-chip event signal) from a multi- function timer peripheral. both external and internal trigger inputs are inter- nally ored, thus avoiding hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. note: the effect of either synchronization mode is to set the start/stop bit, which is reset by hard- ware when in single mode, at the end of each sequence of conversions. requirements: the external synchronisation in- put must receive a low level pulse wider than an intclk period and, for both external and on-chip event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. bit 2 = pow : power up/power down. this bit is set and cleared by software. 0: power down mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: power up mode: the adc converter logic and analog circuitry is enabled. bit 1 = cont : continuous/single . 0: single mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the st bit is set by soft- ware. 1: continuous mode: the first sequence of conver- sions is started, either by software (by setting the st bit), or by hardware (on an internal or ex- ternal trigger, depending on the setting of the intg and extg bits); a continuous conversion sequence is then initiated. bit 0 = st : start/stop. 0: stop conversion. when the adc converter is running in single mode, this bit is hardware re- set at the end of a sequence of conversions. 1: start a sequence of conversions. note: if a write access to this register occurs, the conversion is re-started from the sc[3:0] channel. interrupt control register (ad_icr) the interrupt control register contains the three priority level bits, the two source flags, and their bit mask: interrupt control register (ad_icr) r254 - read/write register page: 63 reset value: 0000 0111 (07h) bit 7 = ecv : end of conversion. this bit is automatically set by hardware after a group of conversions is completed. it must be re- set by the user, before returning from the interrupt service routine. setting this bit by software will cause a software interrupt request to be generat- ed. 0: no end of conversion event occurred 1: an end of conversion event occurred bit 6 = awd : analog watchdog. this is automatically set by hardware whenever ei- ther of the two monitored analog inputs exceeds a threshold. the threshold values are stored in reg- isters r244/r245 and r248/r249 for channel a, and in registers r246/r247 and r250/r251 for channel b respectively. the compare result reg- ister (crr) keeps track of the analog inputs ex- ceeding the thresholds. the awd bit must be reset by the user, before re- turning from the interrupt service routine. setting this bit by software will cause a software interrupt request to be generated. 0: no analog watchdog event occurred 1: an analog watchdog event occurred 70 ecv awd eci awdi x pl2 pl1 pl0 9
370/398 10-bit analog to digital converter (adc) register description (contd) bit 5 = eci : end of conversion interrupt enable. this bit masks the end of conversion interrupt re- quest. 0: mask end of conversion interrupts 1: enable end of conversion interrupts bit 4 = awdi : analog watchdog interrupt enable . this bit masks or enables the analog watchdog interrupt request. 0: mask analog watchdog interrupts 1: enable analog watchdog interrupts bit 3 = reserved. bits 2:0 = pl[2:0]: adc interrupt priority level . these three bits are used to select the interrupt priority level for the adc. interrupt vector register (ad_ivr) r255 - read/write register page: 63 reset value: xxxx xx10 (x2h ) bits 7:2 = v[7:2]: adc interrupt vector. this vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the starting addresses of the adc interrupt service routines. bit 1 = w1 : word select. this bit is set and cleared by hardware, according to the adc interrupt source. 0: interrupt source is the analog watchdog, point- ing to the lower word of the adc interrupt serv- ice block (defined by v[7:2]). 1:interrupt source is the end of conversion inter- rupt, thus pointing to the upper word. note: when two requests occur simultaneously, the analog watchdog request has priority over the end of conversion request, which is held pending. bit 0 = reserved, forced by hardware to 0. 70 v7 v6 v5 v4 v3 v2 w1 0 9
371/398 st92f124/f150/f250 - electrical characteristics 11 electrical characteristics this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v in and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =t a + p d x rthja where: t a = ambient temperature. rthja = package thermal resistance (junction-to ambient). p d = p int + p port . p int =i dd x v dd (chip internal power). p port = port power dissipation (determined by the user) absolute maximum ratings notes : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. all voltages are referenced to v ss = 0 v. note 1: pin injection current occurs when the voltage on any pin exceeds the specified range. note 2: value guaranteed by design. thermal characteristics recommended operating conditions note : (1) > 1mhz when adc or jblpd is used, 2.6mhz when i 2 c is used. symbol parameter value unit v dd supply voltage C 0.3 to 6.5 v av dd adc reference voltage v ss to v dd + 0.3 v av ss adc ground v ss v in input voltage (all pins except pure open drain i/o pins) C 0.3 to v dd + 0.3 v v inod input voltage (pure open drain i/o pins) C 0.3 to 6.5 v v ain analog input voltage (adc inputs) -0.3 to av dd + 0.3 v t stg storage temperature C 55 to +150 c i io load current 10 (2) ma i inj pin injection current - digital and analog inputs (1) 10 (2) ma i tinj absolute sum of all pin injection current in the device 100 (2) ma esd esd susceptibility 2000 v symbol package value unit rthja tqfp64 pqfp100 tqfp100 47 28 44 c/w symbol parameter min max unit t a ambient temperature range 6 suffix version -40 85 c b suffix version -40 105 c suffix version -40 125 v dd operating supply voltage 4.5 5.5 v av dd adc reference voltage 0 v dd + 0.2 v f intclk internal clock frequency 0 (1) 24 mhz c33 stabilization capacitor between v reg and v ss 600 nf 1
372/398 st92f124/f150/f250 - electrical characteristics dc electrical characteristics (v dd = 5 v 10%, t a = C 40 c to +125 c, unless otherwise specified) symbol parameter comment value unit min typ (1) max v ih input high level p0[7:0]-p1[7:0]-p2[7:6]-p2[3:2]- p3.3-p4.2-p4.5-p5.3 ttl 2.0 v cmos 0.7 x v dd v input high level standard schmitt trigger p2[5:4]-p2[1:0]-p3[7:4]-p3[2:0]- p4[4:3]-p4[1:0]-p5[7:4]-p5[2:0]- p6[3:0]-p6[7:6]-p7[7:0]-p8[7:0]- p9[7:0] 0.6 x v dd v input high level high hyst. schmitt trigger p4[7:6]-p6[5:4] 0.7 x v dd (2) v v il input low level p0[7:0]-p1[7:0]-p2[7:6]-p2[3:2]- p3.3-p4.2-p4.5-p5.3 ttl 0.8 v cmos 0.3 x v dd v input low level standard schmitt trigger p2[5:4]-p2[1:0]-p3[7:4] p3[2:0]- p4[4:3]-p4[1:0]-p5[7:4]-p5[2:0]- p6[3:0]-p6[7:6]-p7[7:0]-p8[7:0]- p9[7:0] 0.2 x v dd v input low level high hyst.schmitt trigger p4[7:6]-p6[5:4] 0.25 x v dd v v i input voltage range pure open drain p2[3:2]-p4[7:6] -0.3 6.0 v input voltage range all other pins -0.3 v dd + 0.3 v v hys input hysteresis standard schmitt trigger p2[5:4]-p2[1:0]-p3[7:4]-p3[2:0]- p4[4:3]-p4[1:0]-p5[7:4]-p5[2:0]- p6[3:0]-p6[7:6]-p7[7:0]-p8[7:0]- p9[7:0] 250 mv input hysteresis high hyst. schmitt trigger p4[7:6]-p6[5:4] 1v 1
373/398 st92f124/f150/f250 - electrical characteristics note: (1) unless otherwise stated, typical data are based on t a = 25c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) value guaranteed by design. (3) for a description of the emr1 register - bsz bit refer to the external memory interface chapter. (4) not tested in production, guaranteed by product characterisation. an overload condition occurs when the input voltage on an y pin ex- ceeds the specified voltage range. (5) indicative values extracted from design simulation, 20% to 80% on 50pf load, emr1.bsz bit =0 v oh output high level p6[5:4] (and p0[7:0]-as -ds -rw on st92f150d) push pull mode i oh = C 8ma emr1.bsz bit = 1 (3) v dd C 0.8 v output high level p0[7:0]-p2[7:4]-p2[1:0]-p3[7:0]- p4[5:0]-p5[7:0]-p6[3:0]- p6[7:6]-p7[7:0]-p8[7:0]-p9[7:0]- vpwo-as -ds -rw push pull mode i oh = C 2ma v dd C 0.8 v v ol output low level p4[7:6]-p6[5:4] (and p0[7:0]-p2[3:2]- as -ds -rw on st92f150d) push pull or open drain mode, i ol =8ma, emr1.bsz bit = 1 (3) 0.4 v output low level all pins except oscout push pull or open drain mode, i ol =2ma 0.4 v i wpu weak pull-up current p2[7:4]-p2[1:0]-p3[7:0] p4[7:5]-p4[3:1]-p5.3-p6[7:6]- p6[3:0]-p7[7:0]-p8[7:0]-p9[7:0] bidirectional weak pull-up mode v in = 0v 50 100 300 m a weak pull-up current p6[5:4]-as -ds -rw bidirectional weak pull-up mode v in = 0v 100 220 450 m a i lkio i/o pin input leakage input or tri-state mode, 0v < v in < v dd C 1 + 1 m a i lkiod i/o pin open drain input leakage input or tri-state mode, 0v < v in < v dd C 1 + 1 m a i lkadc adc conv. input leakage C 1 + 1 m a i io load current p4[7:6]-p6[5:4] (and p0[7:0]-p2[3:2]- as - ds -rw on st92f150d) emr1.bsz bit = 1 16 (2) ma p4[7:6]-p6[5:4] (and p0[7:0]-p2[3:2]- as - ds -rw on st92f150d) emr1.bsz bit = 0 4 (2) all other pins except oscout 4 (2) i ov overload current (4) 5 (2) ma sr r slew rate rise (5) 20 30 ns sr f slew rate fall (5) 20 30 ns symbol parameter comment value unit min typ (1) max 1
374/398 st92f124/f150/f250 - electrical characteristics ac electrical characteristics (v dd = 5 v 10%, t a = C 40 c to +125 c, unless otherwise specified) note: all i/o ports are configured in bidirectional weak pull-up mode with no dc load, external clock is driven by a square wave. (1) unless otherwise stated, typical data are based on t a = 25c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) cpu running with code execution from ram memory, all peripherals in reset state, clock input (oscin) driven by external squ are wave. (3) f intclk in [mhz]. (4) current consumption to be added to iddrun when the flash memory is accessed. (5) cpu running with code execution from flash memory, all peripherals running in a typical configuration, clock input (oscin) driven by a 4-mhz crystal = i ddrun + d i dd1 + i dd peripherals (timers, can, etc) (6) value guaranteed by product characterization, not tested in production. (7) current consumption to be added to iddlpwfi when the flash memory is in stand-by mode. (8) flash/e 3 tm in power-down mode, main voltage regulator on = i ddlpr + i ddosc + i dd (standard timer in real time clock mode) (9) the i/os draw a transient current from v dd when an input takes a voltage level in between v ss and v dd . this current is 0 for v in <0.3v or v in >v dd -0.3v, it typically reaches its maximum value when v in is approximatively at v dd /2. symbol parameter intclk typ (1) max unit i ddrun run mode current (2) 24 mhz 45 60 ma any frequency 2.5 + 1.8xf intclk /mhz (3) ma d i dd1 flash / e 3 tm supply current (read) (4) -2 ma d i dd2 flash / e 3 tm supply current (write/erase) (4) -12 ma typical application run mode current (5) 24 mhz 50 ma i ddwfi wfi mode current 24 mhz 14 22 ma any frequency 0.9xf intclk /mhz (3;6) ma d i dd3 flash / e 3 tm supply current (stand-by) (7) -20 m a i ddlpr main voltage regulator power consumption - 300 m a i ddosc crystal oscillator power consumption 200 m a i ddlpwfi low power wfi mode current (8) 4mhz / 32 500 800 m a i ddhalt halt mode current, t a =25c - 1 10 m a i ddtr input transient i dd current (9) - 300 m a 1
375/398 st92f124/f150/f250 - electrical characteristics flash / e 3 tm specifications (v dd = 5v 10%, t a = C 40c to +125c, unless otherwise specified) (1) note: (1) the full range of characteristics will be available after final product characterisation. (2) relational calculation between e 3 tm sector cycling and single byte cycling is provided in a dedicated stmicroelectronics application note (ref. an1152). (3) the maximum value depends on the number of e3 cycles/sector as shown in figure 154 . this maximum value corresponds to the worst case e 3 tm page update, 1 of 4 consecutive write operations at the same e 3 tm address (refer to an1152). figure 154. evolution of worst case e3 page update time parameter min typ max unit main flash byte program 10 250 m s 128 kbytes flash program 1.3 s 64 kbytes flash sector erase 1.5 30 s 128 kbytes flash chip erase 3 s erase suspend latency 15 m s recovery from power-down 10 m s e 3 tm 16 bytes page update (1k e 3 tm ) 30 200 (3) ms e 3 tm chip erase 70 ms reliability flash endurance 25c 10000 cycles flash endurance -40c +125c 3000 e 3 tm endurance 100000 (2) cycles / sector data retention 15 years page update max t a =25c t a =125c 50 10 100 kcycles/sector 100 200 300 1
376/398 st92f124/f150/f250 - electrical characteristics external interrupt timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock p eriod. the value in the right hand two columns shows the timing minimum and maximum for an internal clock at 24mhz (intclk). measurement points are v ih for positive pulses and v il for negative pulses. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 7is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. external interrupt timing wake-up management timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator cloc k period. the value in the right hand two columns show the timing minimum and maximum for an internal clock at 24mhz (intclk). the given data are related to wake-up management unit used in external interrupt mode. measurement points are v ih for positive pulses and v il for negative pulses. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. wake-up management timing n symbol parameter value unit formula min 1 twintlr low level minimum pulse width in rising edge mode 3 tck+10 50 ns 2 twinthr high level minimum pulse width in rising edge mode 3 tck+10 50 ns 3 twinthf high level minimum pulse width in falling edge mode 3 tck+10 50 ns 4 twintlf low level minimum pulse width in falling edge mode 3 tck+10 50 ns n symbol parameter value unit formula min 1 twwkplr low level minimum pulse width in rising edge mode 3 tck+10 50 ns 2 twwkphr high level minimum pulse width in rising edge mode 3 tck+10 50 ns 3 twwkphf high level minimum pulse width in falling edge mode 3 tck+10 50 ns 4 twwkplf low level minimum pulse width in falling edge mode 3 tck+10 50 ns rising edge detection falling edge detection intn n = 0-7 n = 0 - 15 rising edge detection falling edge detection wkupn 1
377/398 st92f124/f150/f250 - electrical characteristics rccu characteristics (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a = 25c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) value guaranteed by design. rccu timing table (v dd = 5v 10%, t a = C 40c to +125c, f intclk = 24 mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a = 25c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) to be valid, a reset pulse must exceed t nfr . all reset glitches with a duration shorter than t frs will be filtered (3) depending on the delay between rising edge of reset pin and the first rising edge of clock1, the value can differ from the typical value for +/- 1 clock1 cycle. legend : t osc = crystal oscilllator clock (clock1) period. pll characteristics (v dd = 5 v 10%, t a = C 40 c to +125 c, f intclk = 24 mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a = 25c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) value guaranteed by design. legend : tosc = crystal oscilllator clock (clock1) period. symbol parameter comment value unit min typ (1) max v ihrs reset input high level input threshold 0.75 x v dd v v ilrs reset input low level input threshold 0.25 x v dd v v irs input voltage range C 0.3 v dd + 0.3 v v hyrs reset input hysteresis 1 (2) v i lkrs reset pin input leakage 0v < v in < v dd C 1 1 m a symbol parameter comment value unit min typ (1) max t frs reset input filtered pulse (2) 50 ns t nfr reset input non filtered pulse (2) 20 m s t rsph (3) reset phase duration 20400 t osc t str stop restart duration div2 = 0 div2 = 1 10200 20400 t osc symbol parameter value unit min typ (1) max f xtl crystal reference frequency 3 5 mhz f vco vco operating frequency 6 24 mhz t plk lock-in time 350 (2) 1000 (2) t osc pll jitter 0 1200 (2) ps pll jitter impact on applicative 500khz signal (can, sci, timers) 0.2 (2) % f pllfree pll free running mode frequency 10 (2) 50 250 (2) khz 1
378/398 st92f124/f150/f250 - electrical characteristics oscillator characteristics (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a = 25 c and v dd = 5v. they are only reported for design guide lines not tested in production. (2) value guaranteed by design. external bus timing table (st92f150d) (v dd = 5 v 10%, t a = C 40 c to +125 c, c load = 50 pf, f intclk = 24 mhz, div2 and/or pll enabled, emr1.bsz bit = 1, unless otherwise specified) notes: the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock pe- riod, prescaler value and number of wait cycles inserted. the values in the right hand two columns show the timing minimum and maximum for an external clock at 24mhz, prescaler value of zero and zero wait states. (1) value guaranteed by design. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. tckh = intclk high pulse width (normally = tck/2) tckl = intclk low pulse width (normally = tck/2) p = clock prescaling value (=prs; division factor = 1+p) wa = wait cycles on as ; = max (p, programmed wait cycles in emr2, requested wait cycles with wait ) wd = wait cycles on ds ; = max (p, programmed wait cycles in wcr, requested wait cycles with wait ) symbol parameter comment value unit min typ (1) max f osc crystal frequency fundamental mode crystal or ex- ternal clock applied to oscout 3 5 mhz g m oscillator transconductance 1.2 (2) 1.5 (2) ma/v v ihck clock input high level external clock 2 (2) v dd + 0.3 v v ilck clock input low level external clock -0.3 0.4 (2) v t stup oscillator start-up time 5 (2) ms i load 100 a r pol 90 128 180 k w v osc oscillation level 600 (2) mv n symbol parameter value (note) unit formula (1) min max 1 tsa (as) address set-up time before as - tck x wa+tckh-9 12 (1) ns 2 thas (a) address hold time after as - tckl-4 17 (1) ns 3 tdas (dr) as - to data available (read) tck x (wd+1)+3 45 (1) ns 4 twas as low pulse width tck x wa+tckh-5 16 (1) ns 5 tdaz (ds) address float to ds 00 (1) ns 6 twds ds low pulse width tck x wd+tckh-5 16 (1) ns 7 tddsr (dr) ds to data valid delay (read) tck x wd+tckh+4 25 (1) ns 8 thdr (ds) data to ds - hold time (read) 7 7 (1) ns 9 tdds (a) ds - to address active delay tckl+11 32 (1) ns 10 tdds (as) ds - to as delay tckl-4 17 (1) ns 11 tsr/w (as) rw set-up time before as - tck x wa+tckh-17 4 (1) ns 12 tddsr (r/w) ds - to rw and address not valid delay tckl-1 20 (1) ns 13 tddw (dsw) write data valid to ds delay -16 -16 (1) ns 14 tsd(dsw) write data set-up before ds - tck x wd+tckh-16 5 (1) ns 15 thds (dw) data hold time after ds - (write) tckl-3 18 (1) ns 16 tda (dr) address valid to data valid delay (read) tck x (wa+wd+1)+tckh-7 55 (1) ns 17 tdas (ds) as - to ds delay tckl-6 15 (1) ns 1
379/398 st92f124/f150/f250 - electrical characteristics external bus timing port9 r port1 a21-a8 1
380/398 st92f124/f150/f250 - electrical characteristics watchdog timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, push-pull output configuration, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 24mhz, with minim um and maximum prescaler value and minimum and maximum counter value. measurement points are v oh or v ih for positive pulses and v ol or v il for negative pulses. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. psc = watchdog prescaler register content (wdtpr): from 0 to 255 cnt = watchdog couter registers content (wdtrh,wdtrl): from 0 to 65535 t wdin = watchdog input signal period (wdin), t wdin 3 8 x tck watchdog timing n symbol parameter value unit formula min max 1 twwdol wdout low pulse width 4 x (psc+1) x (cnt+1) x tck 167 2.8 ns s (psc+1) x (cnt+1) x t wdin 333 ns 2 twwdoh wdout high pulse width 4 x (psc+1) x (cnt+1) x tck 167 2.8 ns s (psc+1) x (cnt+1) x t wdin 333 ns 3 twwdil wdin high pulse width 3 4 x tck 167 ns 4 twwdih wdin low pulse width 3 4 x tck 167 ns 1
381/398 st92f124/f150/f250 - electrical characteristics standard timer timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, push-pull output configuration, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator cloc k period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 24mhz, with minim um and maximum prescaler value and minimum and maximum counter value. measurement points are v oh or v ih for positive pulses and v ol or v il for negative pulses. (1) on this product stin is not available as alternate function but it is internally connected to a precise clock source direct ly derived from the crystal oscillator. refer to rccu chapter for details about clock distribution. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. psc = standard timer prescaler register content (stp): from 0 to 255 cnt = standard timer counter registers content (sth,stl): from 0 to 65535 t stin = standard timer input signal period (stin) , t stin 3 8 x tck standard timer timing n symbol parameter value unit formula min max 1 twstol stout low pulse width 4 x (psc+1) x (cnt+1) x tck 167 2.8 ns s (psc+1) x (cnt+1) x t stin (1) (1) ns 2 twstoh stout high pulse width 4 x (psc+1) x (cnt+1) x tck 167 2.8 ns s (psc+1) x (cnt+1) x t stin (1) (1) ns 3 twstil stin high pulse width 3 4 x tck (1) (1) ns 4 twstih stin low pulse width 3 4 x tck (1) (1) ns 1
382/398 st92f124/f150/f250 - electrical characteristics extended function timer external timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator cloc k period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 24mhz, and minimu m prescaler factor (=2). measurement points are v ih for positive pulses and v il for negative pulses. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. prsc = precsaler factor defined by extended function timer clock control bits (cc1,cc0) on control register cr2 (values: 2,4,8) . extended function timer external timing n symbol parameter value unit formula min 1tw pewl external clock low pulse width (extclk) 3 2 x tck + 10 52 ns 2tw pewh external clock high pulse width (extclk) 3 2 x tck + 10 52 ns 3tw piwl input capture low pulse width (icapx) 3 2 x tck + 10 52 ns 4tw piwh input capture high pulse width (icapx) 3 2 x tck + 10 52 ns 5tw eckd distance between two active edges on extclk 3 4 x tck + 10 177 ns 6tw eicd distance between two active edges on icapx 3 2 x tck x prsc +10 177 ns 1 2 5 extclk 34 6 icapa icapb 1
383/398 st92f124/f150/f250 - electrical characteristics multifunction timer external timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator cloc k period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 24mhz. (1) n = 1 if the input is rising or falling edge sensitive n = 3 if the input is rising and falling edge sensitive (2) in autodiscrimination mode legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. multifunction timer external timing n symbol parameter value unit note formula min max 1tw ctw external clock/trigger pulse width n x tck n x 42 - ns (1) 2tw ctd external clock/trigger pulse distance n x tck n x 42 - ns (1) 3tw aed distance between two active edges 3 x tck 125 - ns 4tw gw gate pulse width 6 x tck 250 - ns 5tw lba distance between tinb pulse edge and the fol- lowing tina pulse edge tck 42 - ns (2) 6tw lab distance between tina pulse edge and the fol- lowing tinb pulse edge 0-ns (2) 7tw ad distance between two txina pulses 0 - ns (2) 8tw owd minimum output pulse width/distance 3 x tck 125 - ns 1
384/398 st92f124/f150/f250 - electrical characteristics sci-m timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. note 1: values guaranteed by product characterization, not tested in production. sci timing n symbol parameter condition value (1) unit min max f rxckin frequency of rxckin 1x mode f intclk / 8 mhz 16x mode f intclk / 4 mhz tw rxckin rxckin shortest pulse 1x mode 4 x tck s 16x mode 2 x tck s f txckin frequency of txckin 1x mode f intclk / 8 mhz 16x mode f intclk / 4 mhz tw txckin txckin shortest pulse 1x mode 4 x tck s 16x mode 2 x tck s 1ts ds ds (data stable) before rising edge of rxckin 1x mode reception with rxckin tck / 2 ns 2td d1 txckin to data out delay time 1x mode transmission with external clock c load < 50pf 2.5 x tck ns 3td d2 clkout to data out delay time 1x mode transmission with clkout 350 ns 1
385/398 st92f124/f150/f250 - electrical characteristics spi timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note: measurement points are v ol , v oh , v il and v ih in the spi timing diagram. (1) values guaranteed by design. legend : tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. n symbol parameter condition value (1) unit min max f spi spi frequency master slave f intclk / 128 0 f intclk / 4 f intclk / 2 mhz 1t spi spi clock period master slave 4 x tck 2 x tck ns 2t lead enable lead time slave 40 ns 3t lag enable lag time slave 40 ns 4t spi_h clock (sck) high time master slave 80 90 ns 5t spi_l clock (sck) low time master slave 80 90 ns 6t su data set-up time master slave 40 40 ns 7t h data hold time (inputs) master slave 40 40 ns 8t a access time (time to data active from high impedance state) slave 0 120 ns 9t dis disable time (hold time to high im- pedance state) 240 ns 10 t v data valid master (before capture edge) slave (after enable edge) tck / 4 120 ns ns 11 t hold data hold time (outputs) master (before capture edge) slave (after enable edge) tck / 4 0 ns ns 12 t rise rise time (20% v dd to 70% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 13 t fall fall time (70% v dd to 20% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 1
386/398 st92f124/f150/f250 - electrical characteristics spi master timing diagram cpha=0, cpol=0 spi master timing diagram cpha=0, cpol=1 spi master timing diagram cpha=1, cpol=0 spi master timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 45 d7-out d6-out d0-out d7-in d6-in d0-in vr000109 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in 1
387/398 st92f124/f150/f250 - electrical characteristics spi slave timing diagram cpha=0, cpol=0 spi slave timing diagram cpha=0, cpol=1 spi slave timing diagram cpha=1, cpol=0 spi slave timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 67 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z d7-out d6-out d0-out d7-in d6-in d0-in vr000112 1
388/398 st92f124/f150/f250 - electrical characteristics i 2 c/ddc-bus timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note: (1) value guaranteed by design. (2) the st9 device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined r egion of the fall- ing edge of scl (3) the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl sign al legend: tck = intclk period = crystal oscillator clock period when clock1 is not divided by 2; 2 x crystal oscillator clock period when clock1 is divided by 2; crystal oscillator clock period x pll factor when the pll is enabled. cb = total capacitance of one bus line in pf freq[2:0] = frequency bits value of i 2 c own address register 2 (i2coar2) i 2 c timing symbol parameter formula protocol specifications unit standard i 2 c fast i 2 c min max min max f intclk internal frequency (slave mode) 2.5 2.5 mhz f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 1.3 m s t high scl clock high period 4.0 0.6 m s t low scl clock low period standard mode fast mode 4.7 1.3 m s t hd:sta hold time start condition. after this period, the first clock pulse is generated t low + tck 4.0 0.6 m s t su:sta set-up time for a repeated start condi- tion t low + t high C t hd:sta 4.7 0.6 m s t hd:dat data hold time freq[2:0] = 000 freq[2:0] = 001 freq[2:0] = 010 freq[2:0] = 011 3 x tck 4 x tck 4 x tck 10 x tck 0 (1;2) 0 (1;2) 0.9 (1;3) ns t su:dat data set-up time (without scl stretching) t low C t hd:dat 250 (1) 100 (1) ns data set-up time (with scl stretch- ing) freq[2:0] = 000 freq[2:0] = 001 freq[2:0] = 010 freq[2:0] = 011 7 x tck 15 x tck 15 x tck 31 x tck t r rise time of both sda and scl signals 1000 (1) 20+0.1cb (1) ns t f fall time of both sda and scl signals 300 (1) 20+0.1cb (1) ns t su:sto set-up time for stop condition t low + t high C t hd:sta 4.0 (1) 0.6 (1) ns cb capacitive load for each bus line 400 400 pf t buf t low p s t hd:sta t hd:dat t r t high t f t su:dat t su:sta sr t hd:sta t sp t su:sto p sda scl 1
389/398 st92f124/f150/f250 - electrical characteristics j1850 byte level protocol decoder timing table (v dd = 5v 10%, t a = C 40c to +125c, c load = 50pf, f intclk = 24mhz, unless otherwise specified) note: (1) values obtained with internal frequency at 24 mhz (intclk), with clksel register set to 23. (2) in transmission mode, symbol durations are compliant to nominal values defined by the j1850 protocol specifications. (3) all values are reported with a precision of 1 m s. j1850 protocol timing symbol parameter value unit note receive mode transmission mode min max nominal t f symbols filtered 0 7- m s (1)(2) t ib invalid bit detected > 7 34 - m s (1)(2) t p0 passive data bit 0 > 34 96 64 m s (1)(2)(3) t a0 active data bit 0 > 96 163 128 m s (1)(2)(3) t p1 passive data bit 1 > 96 163 128 m s (1)(2)(3) t a1 active data bit 1 > 34 96 64 m s (1)(2)(3) t nbs short normalization bit > 34 96 64 m s (1)(2)(3) t nbl long normalization bit > 96 163 128 m s (1)(2)(3) t sof start of frame symbol > 163 239 200 m s (1)(2)(3) t eod end of data symbol > 163 239 200 m s (1)(2)(3) t eof end of frame symbol > 239 - 280 m s (1)(2)(3) t brk break symbol > 239 - 300 m s (1)(2)(3) t idle idle symbol > 280 - 300 m s (1)(2)(3) t nbs t a1 t p0 t eod t sof vpwo t idle t eof t eod vpwo t idle t eof sof 0 short 0 long 1 long 1 short eod nb short eof / idle sof 0 short 0 long 1 long 1 short eod nb long eof / idle t a0 t p1 t a1 t p0 t sof t a0 t p1 t nbl 1
390/398 st92f124/f150/f250 - electrical characteristics 10-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a , unless otherwise specified. figure 155. typical application with adc notes: 1. unless otherwise specified, typical data is based on t a =25c and v dd -v ss =5v. these values are given only as design guidelines and are not tested. 2. v ain may exceed a vss or a vdd . however the conversion result in these cases will be 0000h or ffc0h respectively. 3. any external serial impedance will downgrade the adc accuracy (especially for resistance greater than 10 k w ). data based on characterization results, not tested in production. 4. value guaranteed by design. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 1 4 mhz v ain conversion range voltage (2) av ss av dd v v ainx analog input voltage -0.2 av dd +0.2 r ain external source impedance 10 (3) k w c adc internal sample and hold capacitor 6 (3,4) pf t stab stabilization time after adc enable 10 m s t adc conversion time (sample+hold) f adc = 4 mhz 7 - sample capacitor loading time - hold conversion time 8 20 1/f adc i vdda vdda input current 1 (4) ma ainx c io ~2pf v dd i lkadc 1 m a v ain r ain av dd av ss 0.1 m f v dd adc 1
391/398 st92f124/f150/f250 - electrical characteristics 10-bit adc characteristics (contd) adc accuracy notes: 1. monotonicity and no missing codes are guaranteed by design. 2. refer to figure 156 . for the definition of these parameters. 3. data based on characterization results over the whole temperature range. figure 156. adc accuracy characteristics symbol parameter conditions min max unit monotonicity guaranteed 1) no missing codes guaranteed 1) |e t | total unadjusted error 2) v dd =5.0v 3) av dd =5.0v f adc =4mhz 4 lsb e o offset error 2) -2 2 e g gain error 2) -2 2 |e d | differential linearity error 2) 2 |e l | integral linearity error 2) 3 e o e g 1lsb ideal 1lsb ideal avdd avss C 1024 ----------------------------------------- = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result dihr/dilr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) av dd av ss 1
392/398 st92f124/f150/f250 - general information 12 general information 12.1 ordering information figure 157. device types st92 f 150 j c v 1 q c temperature code : 6 : -40 c to 85 c b: -40c to 105c c: -40 c to 125 c package type : q: pqfp t: tqfp memory size : 2: 256k 1: 128k 9: 64k pin count : v: 100 pins r: 64 pins feature 2 : c: 1 can d: dual (2) can no character: no can feature 1 : no character: no j1850 j: j1850 st sub-family version : f: flash no character: rom st family 1
393/398 st92f124/f150/f250 - general information ordering information (contd) table 70. supported part numbers part number program memory (bytes) ram (bytes) package temperature st92f124r9t6 64k flash 2k tqfp64 -40c to 85c st92f124v1qb 128k flash 4k pqfp100 -40c to 105c st92f150cr1tc tqfp64 -40c to 125c st92f150cv1qb pqfp100 -40c to 105c st92f150cv1tb tqfp100 -40c to 105c st92f150jdv1qc 6k pqfp100 -40c to 125c st92f150jdv1tc tqfp100 st92f250cv2qc 256k flash 8k pqfp100 st92f250cv2qb -40c to 105c st92f250cv2tb tqfp100 -40c to 105c contact st sales office for product availability 1
394/398 st92f124/f150/f250 - general information 12.2 package mechanical data figure 158. 64-pin thin quad flat package figure 159. 100-pin thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 c h l l1 e b a a1 a2 e e1 d d1 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.50 0.020 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 100 h c l l 1 e b a a 2 a1 d d1 e e 1 1
395/398 st92f124/f150/f250 - general information figure 160. 100-pin plastic quad flat package dim. mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.50 0.010 0.020 a2 2.50 2.70 2.90 0.098 0.106 0.114 b 0.22 0.40 0.009 0.016 c 0.11 0.23 0.004 0.009 d 23.20 0.913 d1 20.00 0.787 d2 18.85 0.742 e 17.20 0.677 e1 14.00 0.551 e2 12.35 0.486 e 0.65 0.026 l 0.73 0.88 1.03 0.029 0.035 0.041 number of pins n 100 a a2 a1 b e 0- 7 c 1.60 mm l e e1 e2 d d1 d2 1
396/398 st92f124/f150/f250 - general information 12.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st9 micro- controller family. full details of tools available for the st9 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include realtime kernel software and gang programmers. table 71. stmicroelectronics development tools note 1: the i2c 1 and the general purpose i/os p3.0, p6.6 and p6.7 cannot be emulated by this emulator. since the upper 128kbytes of flash memory are emulated with a ram memory, the programming oper- ations on the f4 and f5 flash sectors are not emulated. 12.3.1 socket and emulator adapter information for information on the type of socket that is sup- plied with st92f150-emu2, refer to the suggest- ed list of sockets in table 72 . note: before designing the board layout, it is rec- ommended to check the overall dimensions of the socket as they may be greater than the dimen- sions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturers datasheet (available from www.ya- maichi.de). table 72. suggested list of socket types supported products emulator programming board st92f124 (tqfp64, tqfp100) st92f150 (tqfp64, tqfp100, pqfp100 st92f250 (1) (tqfp100, pqfp100) st92f150-emu2 st92f150-epb/eu st92f150-epb/us st92f150-epb/uk device socket (supplied with st92f150- emu2) emulator adapter (supplied with st92f150-emu2) tqfp64 14 x14 yamaichi ic149-064-*08-*5 yamaichi icp-064-2 tqfp100 14 x14 yamaichi ic149-100-*25-*5 yamaichi icp-100-5 pqfp100 14 x 20 yamaichi ic149-100-*14-*5 yamaichi icp-100-4-4 1
397/398 st92f124/f150/f250 - summary of changes 13 summary of changes the following is a list of the modifications made to this datasheet. version description of modification date 1.3 added one sales type (st92f124v1) and figure 2 on page 6 changed device summary on page 1 removed ext memory address/data, as , ds , rw , wait , ds2 for tqfp64 versions changed figure 11 on page 16 changed table 2 on page 21 added one sentence at the end of the paragraph using the external interrupt channel for all eft interrupts in section 10.3.4 on page 176 added note in section 10.10.5.7 on page 336 and updated figure 147 changed figure 148 on page 337 updated description of ts2[2:0] bits and ts1[3:0] bits in cbtr1 register ( page 346 ) changed table 70 on page 393. december 02 1
398/398 st92f124/f150/f250 - summary of changes notes : information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 1

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